scholarly journals Complex incremental ΣΔ ADC.

2021 ◽  
Author(s):  
Shaul Peker
Keyword(s):  
Order System ◽  
Cmos Process ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Channel Input ◽  
Switch Capacitor ◽  
Quadrature Phase ◽  
Different Types ◽  
Low Pass ◽  
Time Interleaved

This thesis examines the theory and design of incremental Sigma-Delta (ΣΔ) modulators when applied to complex oversampling analog-to-digital converters (ADCs). Two different types of approaches for the complex ADC are analysed and compared. The first system is a traditional complex bandpass over-sampling ADC with incremental (time limited) ΣΔ architecture. This system uses cross-coupling switch capacitor (SC) integrators and quadrature two channel inputs. The second system uses a low-pass architecture with time interleaved integrators. This system does not have a mismatch between the in-phase and quadrature phase (I/Q) output channels. The input is frequency shifted down to DC during the conversion. A graphical user interface (GUI) design toolbox was created to design and simulate the two types of systems. The bandpass second-order system was fabricated in an IBM 130nm CMOS process with a 83kHz two channel input and 10kHz bandwidth at an OSR of 24.

scholarly journals Complex incremental ΣΔ ADC.

2021 ◽  
Author(s):  
Shaul Peker
Keyword(s):  
Order System ◽  
Cmos Process ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Channel Input ◽  
Switch Capacitor ◽  
Quadrature Phase ◽  
Different Types ◽  
Low Pass ◽  
Time Interleaved

This thesis examines the theory and design of incremental Sigma-Delta (ΣΔ) modulators when applied to complex oversampling analog-to-digital converters (ADCs). Two different types of approaches for the complex ADC are analysed and compared. The first system is a traditional complex bandpass over-sampling ADC with incremental (time limited) ΣΔ architecture. This system uses cross-coupling switch capacitor (SC) integrators and quadrature two channel inputs. The second system uses a low-pass architecture with time interleaved integrators. This system does not have a mismatch between the in-phase and quadrature phase (I/Q) output channels. The input is frequency shifted down to DC during the conversion. A graphical user interface (GUI) design toolbox was created to design and simulate the two types of systems. The bandpass second-order system was fabricated in an IBM 130nm CMOS process with a 83kHz two channel input and 10kHz bandwidth at an OSR of 24.

scholarly journals A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Capacitor Mismatch ◽  
Gain Error ◽  
Spurious Free Dynamic Range ◽  
Time Interleaved ◽  
Free Dynamic

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

scholarly journals A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 305 ◽  
Author(s):  
Dong Wang ◽  
Xiaoge Zhu ◽  
Xuan Guo ◽  
Jian Luan ◽  
Lei Zhou ◽  
...  
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Power Measurement ◽  
Cmos Process ◽  
Analog To Digital ◽  
Full Speed ◽  
Time Interleaved

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

A New Small-Sized Non-Dispersive Infrared (NDIR) Sensor and its Drive/Readout Circuits

2016 ◽  
Author(s):  
Paul C.-P. Chao ◽  
Li-Chi Hsu ◽  
Trong-Hieu Tran
Keyword(s):  
Pulse Width Modulation ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Analog To Digital ◽  
Readout Circuits ◽  
Low Pass ◽  
Driver Circuit ◽  
Module Size ◽  
Gas Chamber

A new miniaturized, non-dispersive, infrared (NDIR) sensor for CO2 intended to be installed in mobile phones and its drive/readout circuits are presented in this study. A typical NDIR sensor consists of three main components; an infrared (IR) light-emitter (light source), a gas chamber, a photo detector (PD) light receiver) and the associated drive/readout circuits. The geometry of the gas chamber is optimized to minimize the total module size to approximately 10 mm × 5 mm × 5 mm, which is much smaller than commercially-available gas sensors. Driver and readout circuits are successfully designed and taped out. The driver circuit intends to generate pulse width modulation (PWM) signal to control proper dimming of LED. The readout circuit, which acquires small signal from photo detector then converts to digital values, includes amplifier, low pass filter and analog-to-digital converter (ADC). The proposed circuit is fabricated by the TSMC 0.35-μm CMOS process, where the area is 4.527 mm2 while power consumption is 60.16 mW for the whole chip. The resolution is less than 12 ppm along with time constant is 0.1 sec.

VCO-BASED CONTINUOUS-TIME SIGMA DELTA ADC BASED ON A DUAL-VCO-QUANTIZER-LOOP STRUCTURE

2013 ◽  
Vol 22 (09) ◽  
pp. 1340013 ◽  
Author(s):  
Z. T. XU ◽  
X. L. ZHANG ◽  
J. Z. CHEN ◽  
S. G. HU ◽  
Q. YU ◽  
...  
Keyword(s):  
Continuous Time ◽  
Signal To Noise Ratio ◽  
Quantization Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Structure ◽  
Signal To Noise ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Adc

This paper explores a continuous time (CT) sigma delta (ΣΔ) analog-to-digital converter (ADC) based on a dual-voltage-controlled oscillator (VCO)-quantizer-loop structure. A third-order filter is adopted to reduce quantization noise and VCO nonlinearity. Even-order harmonics of VCO are significantly reduced by the proposed dual-VCO-quantizer-loop structure. The prototype with 10 MHz bandwidth and 400 MHz clock rate is designed using a 0.18 μm RF CMOS process. Simulation results show that the signal-to-noise ratio and signal-to-noise distortion ratio (SNDR) are 76.9 and 76 dB, respectively, consuming 37 mA at 1.8 V. The key module of the ADC, which is a 4-bit VCO-based quantizer, can convert the voltage signal into a frequency signal and quantize the corresponding frequency to thermometer codes at 400 MS/s.

Design of sigma-delta analog-to-digital converters implemented in 65nm digital CMOS process for LoRa

2017 ◽  
Author(s):  
Doreen Dellosa ◽  
Mel-Jie Bentz del Mundo ◽  
Gelyn Manzanares ◽  
Edrian Daniel Marqueses ◽  
Edzhel Rose Valverde Louis Alarcon ◽  
...  
Keyword(s):  
Analog To Digital Converters ◽  
Cmos Process ◽  
Digital Cmos ◽  
Sigma Delta ◽  
Analog To Digital

Modeling of a 200 KHz Bandwidth Low-pass Switch-capacitor Sigma-delta DAC with a Raised Spur-free Modulator

2017 ◽  
Vol 17 (5) ◽  
pp. 666-674
Author(s):  
Yaya Chen ◽  
Yan Han ◽  
Tianlin Cao ◽  
Xiaoxia Han ◽  
Ray C. C. Cheung ◽  
...  
Keyword(s):  
Sigma Delta ◽  
Switch Capacitor ◽  
Low Pass

A Novel Dual-Mode Low Pass Sigma-Delta Modulator Chip Design for WCDMA and Bluetooth Applications

2013 ◽  
Vol 660 ◽  
pp. 113-118
Author(s):  
Jhin Fang Huang ◽  
Wen Cheng Lai ◽  
Kun Jie Huang ◽  
Ron Yi Liu
Keyword(s):  
Supply Voltage ◽  
Cmos Process ◽  
Dual Mode ◽  
Chip Design ◽  
Loop Filter ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area ◽  
Low Pass ◽  
Σδ Modulator

A dual-mode low pass sigma-delta (ΣΔ) modulator at clock rates of 160 and 100 MHz respectively with cascaded integrators is presented for WCDMA and Bluetooth applications. One of main features is that cascaded integrators with feedback as well as distributed input coupling (CIFB) topology erase a summation amplifier and save power consumption. Another feature is that only one set loop filter is designed by switching capacitors to achieve a dual-mode function and greatly saves chip area. A prototype is fabricated in TSMC 0.18-m CMOS process. At the supply voltage of 1.8 V, measured results have achieved the SNDR of 42/33 dB over 1/2 MHz, respectively for Bluetooth/WCDMA. The chip dissipates a low power of 10.5 mW. Including pads the chip area is only 0.61 (0.71× 0.86) mm².

scholarly journals Phase locked loop-based clock synthesizer for reconfigurable analog-to-digital converters

2021 ◽  
Author(s):  
Mateus B. Castro ◽  
Raphael R. N. Souza ◽  
Agord M. P. Junior ◽  
Eduardo R. Lima ◽  
Leandro T. Manera
Keyword(s):  
Supply Voltage ◽  
Signal To Noise Ratio ◽  
Phase Locked Loop ◽  
Analog To Digital Converters ◽  
Cmos Process ◽  
Reference Frequency ◽  
Process Technology ◽  
Worst Case ◽  
Sigma Delta ◽  
Analog To Digital

AbstractThis paper presents the complete design of a phase locked loop-based clock synthesizer for reconfigurable analog-to-digital converters. The synthesizer was implemented in TSMC 65 nm CMOS process technology and the presented results were obtained from extracted layout view with parasitics. The synthesizer generates clock frequencies ranging from 40 to 230 MHz considering a reference frequency of 10 MHz and a supply voltage of 1.2 V. Worst case current consumption is 634 $$\mu $$ μ W, settling time is 6 $$\mu $$ μ s, maximum jitter is 1.3 ns in a 0.037 mm$$^2$$ 2 area. Performance was validated in a test $$\Sigma \Delta $$ Σ Δ Modulator with bandwidths of 200 kHz, 500 kHz and 2 MHz, and oversampling frequencies of 40, 60 and 80 MHz respectively, with negligible signal-to-noise ratio degradation compared to an ideal clock.

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