OPTIMIZATION STRATEGIES FOR HIGH-LEVEL SYNTHESIS OF CONVOLUTIONAL NEURAL NETWORKS HARDWARE ACCELERATORS

2020 ◽  
Author(s):  
Victor Egiazarian ◽  
Sergei Bykovskii
Keyword(s):  
Neural Networks ◽  
Convolutional Neural Networks ◽  
High Level Synthesis ◽  
Hardware Accelerators ◽  
High Level

scholarly journals Interpretation of Swedish Sign Language Using Convolutional Neural Networks and Transfer Learning

2021 ◽  
Vol 2 (3) ◽  
Author(s):  
Gustaf Halvardsson ◽  
Johanna Peterson ◽  
César Soto-Valero ◽  
Benoit Baudry
Keyword(s):  
Neural Networks ◽  
Sign Language ◽  
Transfer Learning ◽  
Convolutional Neural Networks ◽  
Web Application ◽  
Training Dataset ◽  
Motion Processing ◽  
Image Perception ◽  
Sign Languages ◽  
High Level

AbstractThe automatic interpretation of sign languages is a challenging task, as it requires the usage of high-level vision and high-level motion processing systems for providing accurate image perception. In this paper, we use Convolutional Neural Networks (CNNs) and transfer learning to make computers able to interpret signs of the Swedish Sign Language (SSL) hand alphabet. Our model consists of the implementation of a pre-trained InceptionV3 network, and the usage of the mini-batch gradient descent optimization algorithm. We rely on transfer learning during the pre-training of the model and its data. The final accuracy of the model, based on 8 study subjects and 9400 images, is 85%. Our results indicate that the usage of CNNs is a promising approach to interpret sign languages, and transfer learning can be used to achieve high testing accuracy despite using a small training dataset. Furthermore, we describe the implementation details of our model to interpret signs as a user-friendly web application.

scholarly journals Fully Automatic Cell Segmentation with Fourier Descriptors

2021 ◽  
Author(s):  
Dominik Hirling ◽  
Peter Horvath
Keyword(s):  
Neural Networks ◽  
Convolutional Neural Networks ◽  
Fundamental Problem ◽  
Cell Segmentation ◽  
Fourier Descriptors ◽  
Control Points ◽  
Coefficient Vector ◽  
Fully Automatic ◽  
High Level ◽  
And Control

Cell segmentation is a fundamental problem in biology for which convolutional neural networks yield the best results nowadays. In this paper, we present HarmonicNet, a network, which is a modification of the popular StarDist and SplineDist architectures. While StarDist and SplineDist describe an object by the lengths of equiangular rays and control points respectively, our network utilizes Fourier descriptors, predicting a coefficient vector for every pixel on the image, which implicitly define the resulting segmentation. We evaluate our model on three different datasets, and show that Fourier descriptors can achieve a high level of accuracy with a small number of coefficients. HarmonicNet is also capable of accurately segmenting objects that are not star-shaped, a case where StarDist performs suboptimally according to our experiments.

scholarly journals Automatic Tool for Fast Generation of Custom Convolutional Neural Networks Accelerators for FPGA

Electronics ◽  
2019 ◽  
Vol 8 (6) ◽  
pp. 641 ◽  
Author(s):  
Miguel Rivera-Acosta ◽  
Susana Ortega-Cisneros ◽  
Jorge Rivera
Keyword(s):  
Neural Networks ◽  
Convolutional Neural Networks ◽  
State Of The Art ◽  
Register Transfer Level ◽  
Third Party ◽  
Hardware Accelerators ◽  
Field Programmable ◽  
Custom Hardware ◽  
Architecture Description ◽  
Automatic Tool

This paper presents a platform that automatically generates custom hardware accelerators for convolutional neural networks (CNNs) implemented in field-programmable gate array (FPGA) devices. It includes a user interface for configuring and managing these accelerators. The herein-presented platform can perform all the processes necessary to design and test CNN accelerators from the CNN architecture description at both layer and internal parameter levels, training the desired architecture with any dataset and generating the configuration files required by the platform. With these files, it can synthesize the register-transfer level (RTL) and program the customized CNN accelerator into the FPGA device for testing, making it possible to generate custom CNN accelerators quickly and easily. All processes save the CNN architecture description are fully automatized and carried out by the platform, which manages third-party software to train the CNN and synthesize and program the generated RTL. The platform has been tested with the implementation of some of the CNN architectures found in the state-of-the-art for freely available datasets such as MNIST, CIFAR-10, and STL-10.

scholarly journals FPGA-Based Solution for On-Board Verification of Hardware Modules Using HLS

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2024
Author(s):  
Julián Caba ◽  
Fernando Rincón ◽  
Jesús Barba ◽  
José Antonio de la Torre ◽  
Juan Carlos López
Keyword(s):  
Software Industry ◽  
Design Flow ◽  
High Level Synthesis ◽  
Reconfigurable Systems ◽  
Hardware Accelerators ◽  
Testing Environment ◽  
Development Life Cycle ◽  
Verification Process ◽  
Specialized Hardware ◽  
High Level

High-Level Synthesis (HLS) tools provide facilities for the development of specialized hardware accelerators (HWacc). However, the verification stage is still the longest phase in the development life-cycle. Unlike in the software industry, HLS tools lack testing frameworks that could cover the whole design flow, especially the on-board verification stage of the generated RTL. This work introduces a framework for on-board verification of HLS-based modules by using reconfigurable systems and Docker containers with the aim to automate the verification process and preserve a clean testing environment, making the testbed reusable across different stages of the design flow. Moreover, our solution features a mechanism to check timing requirements of the HWacc. We have applied our solution to the C-kernels of the CHStone Benchmark on a Zedboard, in which the on-board verification process has been accelerated up to four times.

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