scholarly journals On Memory-Block Traversal Problems in Model Checking Timed Systems

2000 ◽  
Vol 7 (3) ◽  
Author(s):  
Fredrik Larsson ◽  
Paul Pettersson ◽  
Wang Yi
Keyword(s):  
Model Checking ◽  
State Space ◽  
Operating Systems ◽  
Memory Management ◽  
Timed Automata ◽  
Model Checker ◽  
Timed Systems ◽  
Memory Block ◽  
Start Up

A major problem in model-checking timed systems is the<br />huge memory requirement. In this paper, we study the memory-block<br />traversal problems of using standard operating systems in exploring the<br />state-space of timed automata. We report a case study which demonstrates<br />that deallocating memory blocks (i.e. memory-block traversal)<br />using standard memory management routines is extremely time-consuming.<br />The phenomenon is demonstrated in a number of experiments by<br />installing the Uppaal tool on Windows95, SunOS 5 and Linux. It seems<br />that the problem should be solved by implementing a memory manager<br />for the model-checker, which is a troublesome task as it is involved in<br />the underlining hardware and operating system. We present an alternative<br />technique that allows the model-checker to control the memory-block<br />traversal strategies of the operating systems without implementing<br />an independent memory manager. The technique is implemented in the<br />Uppaal model-checker. Our experiments demonstrate that it results in<br />significant improvement on the performance of Uppaal. For example, it<br />reduces the memory deallocation time in checking a start-up synchronisation<br />protocol on Linux from 7 days to about 1 hour. We show that the<br />technique can also be applied in speeding up re-traversals of explored<br />state-space.

scholarly journals Linear Parametric Model Checking of Timed Automata

2001 ◽  
Vol 8 (5) ◽  
Author(s):  
Thomas S. Hune ◽  
Judi Romijn ◽  
Mariëlle Stoelinga ◽  
Frits W. Vaandrager
Keyword(s):  
Model Checking ◽  
State Space ◽  
Timed Automata ◽  
Parametric Model ◽  
Model Checker ◽  
Linear Parameter ◽  
Emptiness Problem ◽  
Full Class ◽  
Parameter Constraints ◽  
Published Paper

<p>We present an extension of the model checker Uppaal capable<br /> of synthesizing linear parameter constraints for the correctness of<br />parametric timed automata. The symbolic representation of the (parametric)<br /> state-space is shown to be correct. A second contribution of this<br />paper is the identification of a subclass of parametric timed automata<br />(L/U automata), for which the emptiness problem is decidable, contrary<br />to the full class where it is know to be undecidable. Also we present a<br />number of lemmas enabling the verification effort to be reduced for L/U<br />automata in some cases. We illustrate our approach by deriving linear<br />parameter constraints for a number of well-known case studies from the<br />literature (exhibiting a flaw in a published paper).</p>

Schedulability Analysis for Timed Automata With Tasks

2021 ◽  
Vol 20 (5s) ◽  
pp. 1-26
Author(s):  
Jinghao Sun ◽  
Nan Guan ◽  
Rongxiao Shi ◽  
Guozhen Tan ◽  
Wang Yi
Keyword(s):  
Model Checking ◽  
State Space ◽  
Real Time ◽  
Timed Automata ◽  
Schedulability Analysis ◽  
Scheduling Theory ◽  
Real Time Scheduling ◽  
Analysis Techniques ◽  
Model Complex ◽  
Time Scheduling

Research on modeling and analysis of real-time computing systems has been done in two areas, model checking and real-time scheduling theory. In model checking, an expressive modeling formalism such as timed automata (TA) is used to model complex systems, but the analysis is typically very expensive due to state-space explosion. In real-time scheduling theory, the analysis techniques are highly efficient, but the models are often restrictive. In this paper, we aim to exploit the possibility of applying efficient analysis techniques rooted in real-time scheduling theory to analysis of real-time task systems modeled by timed automata with tasks (TAT). More specifically, we develop efficient techniques to analyze the feasibility of TAT-based task models (i.e., whether all tasks can meet their deadlines on single-processor) using demand bound functions (DBF), a widely used workload abstraction in real-time scheduling theory. Our proposed analysis method has a pseudo-polynomial time complexity if the number of clocks used to model each task is bounded by a constant, which is much lower than the exponential complexity of the traditional model-checking based analysis approach (also assuming the number of clocks is bounded by a constant). We apply dynamic programming techniques to implement the DBF-based analysis framework, and propose state space pruning techniques to accelerate the analysis process. Experimental results show that our DBF-based method can analyze a TAT system with 50 tasks within a few minutes, which significantly outperforms the state-of-the-art TAT-based schedulability analysis tool TIMES.

scholarly journals Is your Model Checker on Time? On the Complexity of Model Checking for Timed Modal Logics

1999 ◽  
Vol 6 (32) ◽  
Author(s):  
Luca Aceto ◽  
Francois Laroussinie
Keyword(s):  
Computational Complexity ◽  
Model Checking ◽  
Timed Automata ◽  
Structural Complexity ◽  
Modal Logics ◽  
System Model ◽  
Model Checker ◽  
Program Complexity

This paper studies the structural complexity of model checking<br />for (variations on) the specification formalisms used in the tools CMC<br />and Uppaal, and fragments of a timed alternation-free mu-calculus. For<br />each of the logics we study, we characterize the computational complexity<br />of model checking, as well as its specification and program complexity,<br />using timed automata as our system model.

Using Timed Automata for Modeling the Clocks of Distributed Embedded Systems

2010 ◽  
pp. 172-193 ◽  
Author(s):  
Guillermo Rodriguez-Navas ◽  
Julian Proenza ◽  
Hans Hansson ◽  
Paul Pettersson
Keyword(s):  
Model Checking ◽  
Embedded Systems ◽  
Embedded System ◽  
Timed Automata ◽  
Model Checker ◽  
Distributed Embedded Systems ◽  
Temporal Behaviour ◽  
System Designer ◽  
Functional Aspects ◽  
Time Systems

Model checking is a widely used technique for the formal verification of computer systems. However, the suitability of model checking strongly depends on the capacity of the system designer to specify a model that captures the real behaviour of the system under verification. For the case of real-time systems, this means being able to realistically specify not only the functional aspects, but also the temporal behaviour of the system. This chapter is dedicated to modeling clocks in distributed embedded systems using the timed automata formalism. The different types of computer clocks that may be used in a distributed embedded system and their effects on the temporal behaviour of the system are introduced, together with a systematic presentation of how the behaviour of each kind of clock can be modeled. The modeling is particularized for the UPPAAL model checker, although it can be easily adapted to other model checkers based on the theory of timed automata.

Verification of Flexray Start-Up Mechanism by Timed Automata

2010 ◽  
Vol 17 (3) ◽  
pp. 461-480 ◽  
Author(s):  
Jan Malinský ◽  
Jiří Novák
Keyword(s):  
Discrete Event Systems ◽  
Timed Automata ◽  
Discrete Event ◽  
Software Tool ◽  
Computation Tree Logic ◽  
Computation Tree ◽  
Event Systems ◽  
Start Up ◽  
Time Parameters

Verification of Flexray Start-Up Mechanism by Timed AutomataThis contribution deals with the modelling of a selected part of a new automotive communication standard called FlexRay. In particular, it focuses on the mechanism ensuring the start-up of a FlexRay network. The model has been created with the use of timed automata and verified. For this purpose the UPPAAL software tool has been used that allows the modelling of discrete event systems with the use of timed automata, and subsequently the verification of the model with the use of suitable queries compiled in the so called computation tree logic. This model can be used to look for incorrect settings of time parameters of communication nodes in the network that prevent network start-up and subsequently the start of the car. The existence of this model also opens the way for finding possible errors in the standard. On the basis of the model, the work gives a case study of the start-up mechanism behaviour verification in a FlexRay network consisting of three communication nodes.

scholarly journals IMITATOR 3: Synthesis of Timing Parameters Beyond Decidability

2021 ◽  
pp. 552-565
Author(s):  
Étienne André
Keyword(s):  
Model Checking ◽  
Real Time ◽  
Timed Automata ◽  
Robustness Analysis ◽  
Parametric Model ◽  
Timing Constraints ◽  
Real Time Systems ◽  
Model Checker ◽  
Time Systems ◽  
Timed Model Checking

AbstractReal-time systems are notoriously hard to verify due to nondeterminism, concurrency and timing constraints. When timing constants are uncertain (in early the design phase, or due to slight variations of the timing bounds), timed model checking techniques may not be satisfactory. In contrast, parametric timed model checking synthesizes timing values ensuring correctness. takes as input an extension of parametric timed automata (PTAs), a powerful formalism to formally verify critical real-time systems. extends PTAs with multi-rate clocks, global rational-valued variables and a set of additional useful features. We describe here the new features and algorithms offered by  3, that moved along the years from a simple prototype dedicated to robustness analysis to a standalone parametric model checker for timed systems.

scholarly journals Model Checking Techniques applied to the design of Web Services

2007 ◽  
Vol 10 (2) ◽  
Author(s):  
Gregorio Dıaz ◽  
Emilia M. Cambronero ◽  
Juan J. Pardo ◽  
Valentın Valero ◽  
Fernando Cuartero
Keyword(s):  
Model Checking ◽  
Web Services ◽  
Timed Automata ◽  
Critical Role ◽  
Verification And Validation ◽  
Time Constraints ◽  
Model Checker

In previous work we have presented the generation of WS-CDL and WS-BPEL documents. In this paper we show the unification of both generations. The aim is to generate correct WS-BPEL skeleton documents from WS-CDL documents by using the Timed Automata as an intermediary model in order to check the correctness of the generated Web Services with Model Checking Techniques. The model checker used is UPPAAL, a well known tool in theoretical and industrial cases that performs the verification and validation of Timed Automata. Note that our interest is focused on Web services where the time constraints play a critical role.

scholarly journals Pemodelan dan Verifikasi Formal Protokol EE-OLSR dengan UPPAAL CORA

2016 ◽  
Vol 10 (1) ◽  
pp. 93
Author(s):  
Rachmat Wahid Saleh Insani ◽  
Reza Pulungan
Keyword(s):  
Model Checking ◽  
Energy Efficient ◽  
Timed Automata ◽  
Packet Transmission ◽  
Model Checker ◽  
Link State ◽  
Internet Users ◽  
Information And Communication ◽  
Fully Automatic ◽  
Verification Process

Information and Communication Technology systems is a most important part of society.  These systems are becoming more and more complex and are massively encroaching on daily life via the Internet and all kinds of embedded systems. Communication protocols are one of the ICT systems used by Internet users. OLSR protocol is a wireless network communication protocol with proactive, and based on link-state algorithm. EE-OLSR protocol is a variant of OLSR that is able to prolong the network lifetime without losses of performance.Protocol verification process generally be done by simulation and testing. However, these processes unable to verify there are no subtle error or design flaw in protocol. Model Checking is an algorithmic method runs in fully automatic to verify a system. UPPAAL is a model checker tool to model, verify, and simulate a system in Timed Automata.UPPAAL CORA is model checker tool to verify EE-OLSR protocol modelled in Linearly Priced Timed Automata, if the protocol satisfy the energy efficient property formulated by formal specification language in Weighted Computation Tree Logic syntax. Model Checking Technique to verify the protocols results in the protocol is satisfy the energy efficient property only when the packet transmission traffic happens.

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