Estimation of hardware and time redundancy when using an additive error vector to correct burst errors in digital data transmission systems

In digital data transmission systems, to improve noise immunity, cyclic codes are widely used, detecting and correcting byte (packet) errors. An error packet is understood to mean errors whose multiplicity does not exceed the number of bits b of the information block. Cyclic codes are used to correct byte errors. The most effective method for correcting byte errors are Reed-Solomon codes, which allow correcting errors in a given number of bytes of information. The main problem of using cyclic (sequential) codes is a long delay time associated with the need to perform a division operation to obtain the remainder, which is not acceptable for digital data transmission systems operating in real time. For example, when using the Reed-Solomon code with a code set length of 69 information bits, the implementation of decoding according to the Euclidean algorithm requires 96 clock cycles, which cannot ensure the channel operation in real time. To eliminate this drawback, one should use codes that correct burst errors that implement an algebraic coding procedure with syndromic decoding of information. However, replacing the cyclic procedure for encoding (decoding) information with a syndromic one leads to a sharp increase in hardware costs associated with the use of a memory unit in the decoder for storing error vector values and a decoder for generating error addresses in accordance with the resulting syndrome. Thus, there is a need to develop a methodological apparatus associated with the construction of a code that corrects errors in a given number of bytes of information and an estimate of the hardware and time costs associated with this purpose. In this work, the need to develop a methodological apparatus associated with the construction of a code that corrects errors in a given number of bytes of information with algebraic syndromic decoding and an assessment of the hardware and time costs associated with this purpose is substantiated. The paper presents the rules for constructing a correcting code that corrects errors in a given number of bytes of information, which implements a linear procedure for constructing a correcting code with syndromic decoding and using an additive error vector, which made it possible to reduce hardware costs for constructing a decoding device (to reduce the amount of memory for storing error vector values). For the developed method for correcting byte errors, expressions for evaluating the number are obtained: checking discharges; additive error vectors that do not require their storage in a memory block; error vectors, for burst errors that occur in adjacent bytes at the same time and require their values to be stored in a memory block. A comparative assessment of hardware and time redundancy in the implementation of the proposed method for correcting packet errors with existing methods is carried out. The proposed method of error correction in a given number of bytes of information with additive formation of the error vector differs from the existing ones in that it allows: carry out the correction of burst errors with algebraic-syndromic decoding (exclude the cyclical procedure for encoding and decoding information); to reduce hardware costs for building a decoding device, since in most cases does not require hardware costs for storing error vectors; to reduce the time spent on encoding and decoding information and to ensure the operation of the data transmission channel in real time; to increase the reliability of the transmitted information by detecting uncorrectable byte errors. Thus, the proposed method for correcting errors in a given number of bytes of information with additive formation of an error vector has a regular and relatively simple procedure for constructing a code, which allows one to reduce the hardware and time costs for encoding and decoding information.

A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory

Purpose This paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle. Design/methodology/approach A new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles. Findings With the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations. Originality/value This is an original paper, which has simultaneously in whole or in part been submitted anywhere else.

PHILOSOPHICAL UNDERSTANDING OF THE ARCHETIPOLOGICAL BLOCK OF MEMORY IN COMPARATIVE ANALYSIS OF K.G. JUNG AND G. POPOV APPROACHES

The current situation related to the necessity of elimination of the consequences of world pandemic and reorganization of the system of professional activity, as one leaves behind the “physical life” preferring it to the world of social networks, Internet platforms, gadgets and electronic artificial limbs, i.e. to the world of hyperreality and virtuality extending, updates and sharply raises questions about the future (what it will be like, how to prepare for it and what skills will be needed). The philosophical understanding of the structure of the archetypological memory block in a comparative analysis of general and diverse approaches of K. G. Jung and G. Popov was carried out. Their theories describe the concept "archetype" and its heuristics in the context of the future of human and reflects mental regularities in one's formation and self-realization in society. G. Popov’s theory about archetypes represents a construct formation of the human future activity line was researched.

ABOUT INTUITION MECHANISMS IN THE CONTEXT OF HUMAN ACTIVITY

The human activity is the object of the conducted research, the mechanisms of intuition is its subject. Therefore, the purpose of this article is statements of a philosophical comprehension of intuition mechanisms functioning in human activity. The main ideas of the author experienced the corresponding approbation in scientific and field researches of 2015-2020. They are systemically stated and presented in this article for the first time, as well. The innovation of the following article consists of the conducted research issues that reflect the systematization of knowledge of the mechanisms of intuition which result in a philosophical comprehension of the principles of operation of human memory blocks. Researches of a dialectic contradiction rational and irrational, activity development sources hold concrete manifestations of a contradiction in an intuition and goal-setting connection, uniting of consciousness and memory. For this reason there comes a requirement to consider the main mechanisms of memory, namely: the prototipology memory block, archetypology memory block, and the ancestral unconscious block which integrity is defined by the memory model.

Encoding of Terms in EMB-Based Mealy FSMs

A method is proposed targeting implementation of FPGA-based Mealy finite state machines. The main goal of the method is a reduction for the number of look-up table (LUT) elements and their levels in FSM logic circuits. To do it, it is necessary to eliminate the direct dependence of input memory functions and FSM output functions on FSM inputs and state variables. The method is based on encoding of the terms corresponding to rows of direct structure tables. In such an approach, only terms depend on FSM inputs and state variables. Other functions depend on variables representing terms. The method belongs to the group of the methods of structural decomposition. The set of terms is divided by classes such that each class corresponds to a single-level LUT-based circuit. An embedded memory block (EMB) generates codes of both classes and terms as elements of these classes. The mutual using LUTs and EMB allows diminishing chip area occupied by FSM circuit (as compared to its LUT-based counterpart). The simple sequential algorithm is proposed for finding the partition of the set of terms by a determined number of classes. The method is based on representation of an FSM by a state transition table. However, it can be used for any known form of FSM specification. The example of synthesis is shown. The efficiency of the proposed method was investigated using a library of standard benchmarks. We compared the proposed with some other known design methods. The investigations show that the proposed method gives better results than other discussed methods. It allows the obtaining of FSM circuits with three levels of logic and regular interconnections.

Economy Mode Setting Device for Wind-Diesel Power Plants

The article is devoted to the problem of reducing fuel consumption in a diesel generator set (DGS) as a part of a wind-diesel power plant (WDPP). The object of the research is a variable speed DGS. The goal is to develop the WDPP intelligent control system, providing an optimal shaft speed of an internal combustion engine (ICE). The basis of the intelligent control system is an economy mode setting device (EMSD), which controls the fuel supply to the ICE. The functional chart of EMSD has been presented. The main EMSD blocks contain a controller and an associative memory block. The associative memory block is a software model of an artificial neural network that determines the optimal shaft speed of the ICE. An algorithm for the WDPP intelligent control system has been developed and tested using the WDPP Simulink model. The EMSD prototype has been created, and its research has been conducted. Dependences of the change in specific and absolute fuel consumption on the load power have been obtained for two 4 kW DGS: with constant rotation speed and variable rotation speed DGS with EMSD. It has been established that the use of EMSD in the mode of low loads allow one to reduce fuel consumption by almost 30%. The error in determining the optimal engine speed using EMSD prototype is not more than 15%.