Multi-Level Phase Change Memory Cells with SiN or Ta2O5Barrier Layers

2012 ◽  
Vol 51 (2S) ◽  
pp. 02BD08 ◽  
Author(s):  
Ashvini Gyanathan ◽  
Yee-Chia Yeo
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Memory Cells ◽  
Multi Level ◽  
Change Memory

scholarly journals Enhancing Programming Variability in Multi-Bit Phase Change Memory Cells for Security

2020 ◽  
Vol 19 ◽  
pp. 820-828
Author(s):  
Nafisa Noor ◽  
Sadid Muneer ◽  
Raihan Sayeed Khan ◽  
Anna Gorbenko ◽  
Helena Silva
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Memory Cells ◽  
Change Memory

scholarly journals Speeding Up the Write Operation for Multi-Level Cell Phase Change Memory with Programmable Ramp-Down Current Pulses

Micromachines ◽  
2019 ◽  
Vol 10 (7) ◽  
pp. 461 ◽  
Author(s):  
Chenchen Xie ◽  
Xi Li ◽  
Houpeng Chen ◽  
Yang Li ◽  
Yuanguang Liu ◽  
...  
Keyword(s):  
Phase Change ◽  
Current Source ◽  
Phase Change Memory ◽  
Operation Time ◽  
Access Time ◽  
Fully Differential ◽  
Current Pulses ◽  
Multi Level ◽  
The Impact ◽  
Change Memory

Multi-level cell (MLC) phase change memory (PCM) can not only effectively multiply the memory capacity while maintaining the cell area, but also has infinite potential in the application of the artificial neural network. The write and verify scheme is usually adopted to reduce the impact of device-to-device variability at the expense of a greater operation time and more power consumption. This paper proposes a novel write operation for multi-level cell phase change memory: Programmable ramp-down current pulses are utilized to program the RESET initialized memory cells to the expected resistance levels. In addition, a fully differential read circuit with an optional reference current source is employed to complete the readout operation. Eventually, a 2-bit/cell phase change memory chip is presented with a more efficient write operation of a single current pulse and a read access time of 65 ns. Some experiments are implemented to demonstrate the resistance distribution and the drift.

Multi-level phase-change memory with ultralow power consumption and resistance drift

2021 ◽  
Author(s):  
Bin Liu ◽  
Kaiqi Li ◽  
Wanliang Liu ◽  
Jian Zhou ◽  
Liangcai Wu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Phase Change ◽  
Phase Change Memory ◽  
Multi Level ◽  
Ultralow Power ◽  
Change Memory

Modeling of Set and Reset Operations of Phase-Change Memory Cells

2011 ◽  
Vol 32 (12) ◽  
pp. 1737-1739 ◽  
Author(s):  
Azer Faraclas ◽  
Nicholas Williams ◽  
Ali Gokirmak ◽  
Helena Silva
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Memory Cells ◽  
Change Memory

Surface-Tensile-Stress Induced Polishing-Voids Suppression via H2O2 Oxidizer Effect in Cross-Point Phase-Change-Memory-Cells

2019 ◽  
Vol 8 (11) ◽  
pp. P667-P672
Author(s):  
Soo-Bum Kim ◽  
Hao Cui ◽  
Jong-Young Cho ◽  
Eun-Bin Seo ◽  
Sang-Su Yun ◽  
...  
Keyword(s):  
Tensile Stress ◽  
Phase Change ◽  
Phase Change Memory ◽  
Memory Cells ◽  
Cross Point ◽  
Change Memory

Two-bit cell operation in diode-switch phase change memory cells with 90nm technology

2008 ◽  
Author(s):  
D.-H. Kang ◽  
J.-H. Lee ◽  
J.H. Kong ◽  
D. Ha ◽  
J. Yu ◽  
...  
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Memory Cells ◽  
Change Memory
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