A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

2016 ◽  
Vol 55 (4S) ◽  
pp. 04EF15 ◽  
Author(s):  
Yitao Ma ◽  
Sadahiko Miura ◽  
Hiroaki Honjo ◽  
Shoji Ikeda ◽  
Takahiro Hanyu ◽  
...  
2011 ◽  
Vol 10 (11) ◽  
pp. 2161-2167 ◽  
Author(s):  
Jianping Hu ◽  
Xiaoying Yu ◽  
Jindan Chen

SPIN ◽  
2013 ◽  
Vol 03 (04) ◽  
pp. 1340014 ◽  
Author(s):  
TAKAHIRO HANYU

This paper presents an architecture-level approach, called nonvolatile logic-in-memory (NV-LIM) architecture, to solving performance-wall and power-wall problems in the present CMOS-only-based logic-LSI (Large-Scaled Integration) processors. The use of magnetic tunnel junction devices combined with a CMOS-gate style makes it possible to achieve a high-performance and ultra-low-power logic LSI. Some concrete examples using the proposed method allow you to achieve the desired performance improvement compared to a corresponding CMOS-only-based realization.


2014 ◽  
Vol 61 (6) ◽  
pp. 1755-1765 ◽  
Author(s):  
Djaafar Chabi ◽  
Weisheng Zhao ◽  
Erya Deng ◽  
Yue Zhang ◽  
Nesrine Ben Romdhane ◽  
...  

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