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A Novel Match-line Charging Control Scheme with a New Sense Amplifier for High-Speed and Low-Power Content-Addressable Memory
Mapping Intimacies
◽
10.7567/ssdm.2008.p-5-9
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2008
◽
Author(s):
M. Hasan
◽
T. Rahman
◽
N. Hasan
◽
A. B. M. H. Rashid
◽
A. R. Patwary
Keyword(s):
Low Power
◽
High Speed
◽
Content Addressable Memory
◽
Sense Amplifier
◽
Control Scheme
◽
Charging Control
◽
Power Content
Download Full-text
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Low-Power Content Addressable Memory Using 2N-2N2P Circuits
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2006
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Sense Amplifiers
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Low-power content addressable memory design using two-layer P-N match-line control and sensing
Integration
◽
10.1016/j.vlsi.2020.06.001
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2020
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◽
pp. 73-84
Author(s):
Sheikh Wasmir Hussain
◽
Telajala Venkata Mahendra
◽
Sandeep Mishra
◽
Anup Dandapat
Keyword(s):
Low Power
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Content Addressable Memory
◽
Memory Design
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Low-power content-addressable memory design using a double match-line (DML) architecture
2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)
◽
10.1109/mwscas.2013.6674676
◽
2013
◽
Author(s):
Ya-Chun Lin
◽
Yen-Jen Chang
◽
Tung-Chi Wu
Keyword(s):
Low Power
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Content Addressable Memory
◽
Memory Design
◽
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1.5 V high speed low power CMOS current sense amplifier
Electronics Letters
◽
10.1049/el:19951351
◽
1995
◽
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◽
pp. 1991-1993
◽
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Author(s):
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◽
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A Low Power Content Addressable Memory Using Low Swing Search Lines
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◽
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◽
2011
◽
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◽
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◽
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Byung-Do Yang
◽
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◽
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◽
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...
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Content Addressable Memory
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Static divided word matching line for low-power Content Addressable Memory design
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
◽
10.1109/iscas.2004.1329350
◽
2004
◽
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Author(s):
Kuo-Hsing Cheng
◽
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◽
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Low Power
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Content Addressable Memory
◽
Memory Design
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A Low-Power Content-Addressable Memory (CAM) using Pipelined Search Scheme
Technological Developments in Networking, Education and Automation
◽
10.1007/978-90-481-9151-2_71
◽
2010
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pp. 405-410
Author(s):
Yibo Song
◽
Zheng Yao
◽
Xingguo Xiong
Keyword(s):
Low Power
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Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports
Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
◽
10.1007/978-3-540-74442-9_8
◽
2007
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pp. 75-85
Author(s):
Saleh Abdel-Hafeez
◽
Shadi M. Harb
◽
William R. Eisenstadt
Keyword(s):
Low Power
◽
Content Addressable Memory
◽
Power Content
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