Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) ◽

10.1109/icecs.2012.6463706 ◽

2012 ◽

Author(s):

Vinicius dos S. Livramento ◽

Chrystian Guth ◽

Jose Luis Guntzel ◽

Marcelo O. Johann

Keyword(s):

Lagrangian Relaxation ◽

Leakage Power ◽

Gate Sizing ◽

Power Minimization ◽

Discrete Gate Sizing

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Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ◽

10.1109/isvlsi.2019.00059 ◽

2019 ◽

Author(s):

Henrique Placido ◽

Ricardo Reis

Keyword(s):

Lagrangian Relaxation ◽

Gate Sizing ◽

Discrete Gate Sizing

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Fast and Efficient Lagrangian Relaxation-Based Discrete Gate Sizing

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013 ◽

10.7873/date.2013.370 ◽

2013 ◽

Author(s):

Vinicius S. Livramento ◽

Chrystian Guth ◽

Jose Luis Guntzel ◽

Marcelo O. Johann

Keyword(s):

Lagrangian Relaxation ◽

Gate Sizing ◽

Discrete Gate Sizing

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A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/2647956 ◽

2014 ◽

Vol 19 (4) ◽

pp. 1-25 ◽

Author(s):

Vinicius S. Livramento ◽

Chrystian Guth ◽

José Luís Güntzel ◽

Marcelo O. Johann

Keyword(s):

Lagrangian Relaxation ◽

Gate Sizing ◽

Hybrid Technique ◽

Discrete Gate Sizing

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Incremental Lagrangian Relaxation based Discrete Gate Sizing and Threshold Voltage Assignment

2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST) ◽

10.1109/mocast52088.2021.9493338 ◽

2021 ◽

Author(s):

Dimitrios Mangiras ◽

Giorgos Dimitrakopoulos

Keyword(s):

Lagrangian Relaxation ◽

Threshold Voltage ◽

Gate Sizing ◽

Discrete Gate Sizing

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The epsilon-approximation to discrete VT assignment for leakage power minimization

Proceedings of the 2009 International Conference on Computer-Aided Design - ICCAD '09 ◽

10.1145/1687399.1687453 ◽

2009 ◽

Author(s):

Yujia Feng ◽

Shiyan Hu

Keyword(s):

Leakage Power ◽

Power Minimization

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Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004. ◽

10.1109/iccad.2004.1382535 ◽

2005 ◽

Author(s):

D. Sinha ◽

Hai Zhou

Keyword(s):

Lagrangian Relaxation ◽

Gate Sizing ◽

Timing Constraints ◽

Crosstalk Reduction

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Sensitivity-guided metaheuristics for accurate discrete gate sizing

Proceedings of the International Conference on Computer-Aided Design - ICCAD '12 ◽

10.1145/2429384.2429428 ◽

2012 ◽

Author(s):

Jin Hu ◽

Andrew B. Kahng ◽

SeokHyeong Kang ◽

Myung-Chul Kim ◽

Igor L. Markov

Keyword(s):

Gate Sizing ◽

Discrete Gate Sizing

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Leakage Power Minimization

Low-Power VLSI Circuits and Systems ◽

10.1007/978-81-322-1937-8_9 ◽

2014 ◽

pp. 261-302

Author(s):

Ajit Pal

Keyword(s):

Leakage Power ◽

Power Minimization

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Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment

2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing ◽

10.1109/euc.2008.90 ◽

2008 ◽

Author(s):

Meikang Qiu ◽

Jiande Wu ◽

Jingtong Hu ◽

Yi He ◽

Edwin H.-M. Sha

Keyword(s):

Leakage Power ◽

Power Minimization

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Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization

2007 44th ACM/IEEE Design Automation Conference ◽

10.1109/dac.2007.375129 ◽

2007 ◽

Author(s):

De-Shiuan Chiou ◽

Da-Cheng Juan ◽

Yu-Ting Chen ◽

Shih-Chieh Chang

Keyword(s):

Leakage Power ◽

Power Minimization ◽

Fine Grained ◽

Transistor Sizing

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