resistive bridges Recently Published Documents

Process Variation-Aware Test for Resistive Bridges

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2009.2021728 ◽

2009 ◽

Vol 28 (8) ◽

pp. 1269-1274 ◽

Cited By ~ 22

Author(s):

U. Ingelsson ◽

B.M. Al-Hashimi ◽

S. Khursheed ◽

S.M. Reddy ◽

P. Harrod

Keyword(s):

Process Variation ◽

Accurate modeling and fault simulation of Byzantine resistive bridges

2007 25th International Conference on Computer Design ◽

10.1109/iccd.2007.4601923 ◽

2007 ◽

Author(s):

Hugo Cheung ◽

Sandeep K. Gupta

Keyword(s):

Fault Simulation ◽

SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges

16th Asian Test Symposium (ATS 2007) ◽

10.1109/ats.2007.71 ◽

2007 ◽

Cited By ~ 7

Author(s):

Piet Engelke ◽

Bettina Braitling ◽

Ilia Polian ◽

Michel Renovell

Keyword(s):

Parallel Evaluation ◽

SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges

16th Asian Test Symposium (ATS 2007) ◽

10.1109/ats.2007.4388050 ◽

2007 ◽

Author(s):

Piet Engelke ◽

Bettina Braitling ◽

Ilia Polian ◽

Michel Renovell

Keyword(s):

Parallel Evaluation ◽

Test Generation for Weak Resistive Bridges

2006 15th Asian Test Symposium ◽

10.1109/ats.2006.261030 ◽

2006 ◽

Author(s):

Shahdad Irajpour ◽

Sandeep Gupta ◽

Melvin Breuer

Keyword(s):

Test Generation ◽

Diagnosis of delay faults due to resistive bridges, delay variations and defects

2006 15th Asian Test Symposium ◽

10.1109/ats.2006.261023 ◽

2006 ◽

Author(s):

Lei Wang ◽

Sandeep Gupta ◽

Melvin Breuer

Keyword(s):

Delay Faults ◽

Delay Variations ◽

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) ◽

Automatic path-delay fault test generation for combined resistive vias, resistive bridges, and capacitive crosstalk delay faults

10.1109/vlsid.2006.51 ◽

2006 ◽

Author(s):

S. Chary ◽

M.L. Bushnell

Keyword(s):

Test Generation ◽

Delay Faults ◽

Path Delay ◽

Delay Fault ◽

Path Delay Fault ◽

19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) ◽

Analog macromodeling for combined resistive vias, resistive bridges, and capacitive crosstalk delay faults

10.1109/vlsid.2006.47 ◽

2006 ◽

Cited By ~ 4

Author(s):

S. Chary ◽

M.L. Bushnell

Keyword(s):

Delay Faults ◽

A circuit level fault model for resistive bridges

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/944027.944036 ◽

2003 ◽

Vol 8 (4) ◽

pp. 546-559 ◽

Cited By ~ 29

Author(s):

Zhuo Li ◽

Xiang Lu ◽

Wangqi Qiu ◽

Weiping Shi ◽

D. M. H. Walker

Keyword(s):

Fault Model ◽