Blind Recognition of Parameters of Reed Solomon Code from Intercepted Erroneous Codewords

Error correcting codes are designed for reliable transmission of digital information over a noisy channel. Several papers have been published on blind identification of binary FEC codes but papers reported on the identification of non-binary error correcting codes are less. Due to its strong error correction capability, RS (Reed-Solomon) code is being used widely. So technique for blind recognition of RS code is required to analyse intercepted signal as well as for intelligent communication. This paper presents a technique for extraction of parameters of Reed-Solomon code from intercepted demodulated bitstream. The proposed algorithm is very simple and hence it is very practical for hardware implementation. Our approach has been verified using MATLAB simulation.

Performance of a parallel Hamming coding in short-frame OFDM sensor's network

In this paper, we focus on the most relevant Error Correcting Codes (ECCs): the Hamming code and the Reed-Solomon code in order to meet the trade-off between the low implementation complexity and the high error correction capacity in a short-frame OFDM communication system. Moreover, we discuss and validate via simulations this trade-off between complexity (Hamming is the easiest to code) and error correction capability (Reed-Solomon being the most effective). Therefore, we have to either improve the correction capacity of the Hamming code, or decrease the complexity cost for the Reed-Solomon code. Based on this analysis, we propose a new design of parallel Hamming coding. On the one hand, we validate this new model of parallel Hamming coding with numerical results using MATLAB-Simulink tools and BERTool Application which makes easier the Bit Error Rate (BER) performance simulations. On the other hand, we implement the design of this new model on an FPGA mock-up and we show that this solution of a parallel Hamming encoder/decoder uses a few resources (LUTs) and has a higher capability of correcting when compared to the simple Hamming code.

Addressing multiple bit/symbol errors in DRAM subsystem

As DRAM technology continues to evolve towards smaller feature sizes and increased densities, faults in DRAM subsystem are becoming more severe. Current servers mostly use CHIPKILL based schemes to tolerate up-to one/two symbol errors per DRAM beat. Such schemes may not detect multiple symbol errors arising due to faults in multiple devices and/or data-bus, address bus. In this article, we introduce Single Symbol Correction Multiple Symbol Detection (SSCMSD)—a novel error handling scheme to correct single-symbol errors and detect multi-symbol errors. Our scheme makes use of a hash in combination with Error Correcting Code (ECC) to avoid silent data corruptions (SDCs). We develop a novel scheme that deploys 32-bit CRC along with Reed-Solomon code to implement SSCMSD for a ×4 based DDR4 system. Simulation based experiments show that our scheme effectively guards against device, data-bus and address-bus errors only limited by the aliasing probability of the hash. Our novel design enabled us to achieve this without introducing additional READ latency. We need 19 chips per rank, 76 data bus-lines and additional hash-logic at the memory controller.