scholarly journals Performance of a parallel Hamming coding in short-frame OFDM sensor's network

2021 ◽  
Vol 2 (1) ◽  
pp. 77-88
Author(s):  
Jorge Fernandez-Mayoralas ◽  
Raouia Masmoudi Ghodhbane
Keyword(s):  
Error Correction ◽  
Error Correcting Codes ◽  
Hamming Code ◽  
Trade Off ◽  
New Model ◽  
Solomon Code ◽  
Error Correction Capability ◽  
Reed Solomon Code ◽  
Complexity Cost ◽  
The One

In this paper, we focus on the most relevant Error Correcting Codes (ECCs): the Hamming code and the Reed-Solomon code in order to meet the trade-off between the low implementation complexity and the high error correction capacity in a short-frame OFDM communication system. Moreover, we discuss and validate via simulations this trade-off between complexity (Hamming is the easiest to code) and error correction capability (Reed-Solomon being the most effective). Therefore, we have to either improve the correction capacity of the Hamming code, or decrease the complexity cost for the Reed-Solomon code. Based on this analysis, we propose a new design of parallel Hamming coding. On the one hand, we validate this new model of parallel Hamming coding with numerical results using MATLAB-Simulink tools and BERTool Application which makes easier the Bit Error Rate (BER) performance simulations. On the other hand, we implement the design of this new model on an FPGA mock-up and we show that this solution of a parallel Hamming encoder/decoder uses a few resources (LUTs) and has a higher capability of correcting when compared to the simple Hamming code.

scholarly journals Blind Recognition of Parameters of Reed Solomon Code from Intercepted Erroneous Codewords

2021 ◽  
Vol 71 (6) ◽  
pp. 772-776
Author(s):  
Anand Sharma ◽  
Praneesh Gupta
Keyword(s):  
Hardware Implementation ◽  
Error Correcting Codes ◽  
Digital Information ◽  
Matlab Simulation ◽  
Solomon Code ◽  
Rs Code ◽  
Error Correction Capability ◽  
Reed Solomon Code ◽  
Intelligent Communication ◽  
Blind Recognition

Error correcting codes are designed for reliable transmission of digital information over a noisy channel. Several papers have been published on blind identification of binary FEC codes but papers reported on the identification of non-binary error correcting codes are less. Due to its strong error correction capability, RS (Reed-Solomon) code is being used widely. So technique for blind recognition of RS code is required to analyse intercepted signal as well as for intelligent communication. This paper presents a technique for extraction of parameters of Reed-Solomon code from intercepted demodulated bitstream. The proposed algorithm is very simple and hence it is very practical for hardware implementation. Our approach has been verified using MATLAB simulation.

Study on the Decoder for Reed-Solomon (255, 239) Code

2013 ◽  
Vol 482 ◽  
pp. 390-393
Author(s):  
Yue Tao Ge ◽  
Xiao Ming Liu ◽  
Xiao Tong Yin
Keyword(s):  
Error Correction ◽  
Serial Port ◽  
Hardware Platform ◽  
Solomon Code ◽  
Serial Port Communication ◽  
Fast Speed ◽  
Error Correction Capability ◽  
Reed Solomon Code ◽  
To Receive ◽  
Input Error

Reed Solomon code is described as a theoretical decoder that corrected errors by finding the most popular message polynomial. The Verilog language is applied to descript decoding algorithm. Cyclone series FPGA EP1C6Q240C8 is adopted as a core of hardware platform and a serial port communication part is used to receive input error correction data. The results show that it can successfully correct eight errors, which is the limitation of error correction. With the RS decoder, it can ensure that the strong error correction capability and fast speed.

scholarly journals Modified Welch Berlekamp Algorithm to Decode Reed Solomon Codes

2018 ◽  
Vol 164 ◽  
pp. 01003
Author(s):  
Ali Mahmudi ◽  
Sentot Achmadi ◽  
Michael
Keyword(s):  
Error Correction ◽  
Hardware Description Language ◽  
Description Language ◽  
Solomon Code ◽  
Reed Solomon Codes ◽  
Reed Solomon Code ◽  
Hardware Description ◽  
Pilot Design ◽  
Xilinx Fpga

In this paper, the Reed Solomon Code is decoded using the Welch-Berlekamp Algorithm. The RS Decoder is implemented using Hardware Description Language VHDL (VHSIC hardware Description Language) and simulated on Modelsim software. Some modifications have been carried out on the Welch Berlekamp algorithm in such a way that it is easier to implement. A pilot design double error correction RS(63, 59) decoder has been written in VHDL and simulated. The XILINX FPGA layout RS(63, 59) is then obtained.

Getting Over Athens

2018 ◽  
Author(s):  
Nicolas Wiater
Keyword(s):  
Roman Empire ◽  
The Other ◽  
The Political ◽  
New Model ◽  
Dionysius Of Halicarnassus ◽  
The One

This chapter examines the ambivalent image of Classical Athens in Dionysius of Halicarnassus’ Roman Antiquities. This image reflects a deep-seated ambiguity of Dionysius’ Classicist ideology: on the one hand, there is no question for Dionysius that Athenocentric Hellenicity failed, and that the Roman empire has superseded Athens’ role once and for all as the political and cultural centre of the oikoumene. On the other, Dionysius accepted Rome’s supremacy as legitimate partly because he believed (and wanted his readers to believe) her to be the legitimate heir of Classical Athens and Classical Athenian civic ideology. As a result, Dionysius develops a new model of Hellenicity for Roman Greeks loyal to the new political and cultural centre of Rome. This new model of Greek identity incorporates and builds on Classical Athenian ideals, institutions, and culture, but also supersedes them.

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