As part of the development CAD for design rule checks (DRC), it is necessary to use logical operations on orthogonal polygons that form the layout of an integrated circuit. Such operations as union, intersection, subtraction are performed over layers that contain orthogonal polygons. These operations are subject to stringent execution time requirements. The traditional representation of polygons in the form of bitmaps does not provide a quasi-linear dependence of time on the processed data size and requires development of new algorithms and polygon representation approaches. This paper contains a description of a modified sweeping line obscuring algorithm that achieves O(N log N) time. The algorithm uses three properties of the polygon: the separation of inner region from outer region by the edge, the belonging of edges to the set of either vertical or horizontal edges, and dissection of the layer plane into rectangular fragments which belong to either inner or outer region of the polygon. Procedures of input polygon contour representations that are dissected into sets of vertical and horizontal edges are described. As a result of performing logical operations, polygon edges of the resulting layer are formed. These edges, in turn, are converted into contour representations. The results of a computational experiment confirming the nature of the time dependences determined theoretically are presented. We propose the structure of a software system for DRC, built with the use of programming languages C++ and Lua.
Algorithm for Implementing Logical Operations on Sets of Orthogonal Polygons
