A Low Native Jitter Voltage Controlled Oscillator on 0.18μm CMOS Process

In this thesis, a kind of jitter is focused on, which is called Native Jitter (NJ) of the Voltage Controlled Oscillator (VCO). The cause of NJ is the high order effect of the transistor itself in the VCO, and almost has no correlation with the control voltage or supply. The detailed analysis of the cause and the evaluation of this NJ is proposed in this paper, and an Inter-locked Dual-loop VCO (ID-VCO) is put forward, in which most of the NJ is eliminated. A test chip of the ID-VCO based on 0.18μm CMOS process is established. Compared with the classical single end VCO, the result shows that the peak to peak value and mean-root-square values of period jitter reduce 15.4% and 16.3%, the same values of cycle-to-cycle jitter reduce 9.82% and 6.98%, respectively.