Energy Efficient Light Weight Security Algorithm for Low Power IOT Devices

Internet of Things (IoT) is the state of art which connects, communicates, intelligently resolves and processes data between physical devices and smart phone or to a centralized server. Billions of users are centrally coordinated via the internet. The number of ubiquitous IoT devices will surpass the number of humans. For secured data transfer, IoT requires strenuous focus on security. Inspite of the secured IoT layered approach integrated in its architecture, yet they are susceptible to thwarting attacks. With proliferating applications and innovations, there is a stringent need to preserve user privacy and anonymize interactions using a lightweight cryptographic algorithm. Existing cryptographic algorithms have constraints on power, limited battery, real time execution, latency, code length and memory. In this research, initially comparison of the existing algorithms is made. Subsequently, Augmented Security and Optimized memory space is achieved for the data channelized via IoT by using the combination of the Light weight masked AES (Advanced Encryption Standard) and MD5 (Message Digest) hash algorithm. This chaining technique is implemented using VHDL Coding, Xilinx ISE and ModelSim 6.5 software tool. In the proposed algorithm, area, power and timing factors are reduced using optimization techniques, which drastically reduces the power consumed, and chip area. Chip area is calculated in terms of gate equivalents and power consumption is reduced through clock gating and operand isolation techniques.

Power Optimization Using Clock Gating and Power Gating

The scaling of CMOS technology has continued due to ever increasing demand of greater performance with low power consumption. This demand has grown further by the portable and battery operated devices market. To meet the challenge of greater energy efficiency and performance, a number of power optimization techniques at processor and system components level are proposed by the research community such as clock gating, operand isolation, memory splitting, power gating, dynamic voltage and frequency scaling, etc. This chapter reviews advancements in the dynamic power optimization techniques like clock gating and power gating. This chapter also reviews some architectures and optimization techniques that have been developed for greater power reduction without any significant performance degradation or area cost.