Power Optimization Using Clock Gating and Power Gating

2016 ◽  
pp. 1-20
Author(s):  
Arsalan Shahid ◽  
Saad Arif ◽  
Muhammad Yasir Qadri ◽  
Saba Munawar
Keyword(s):  
Power Optimization ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Power Gating ◽  
Clock Gating ◽  
Dynamic Voltage ◽  
Significant Performance ◽  
Operand Isolation ◽  
Increasing Demand ◽  
And Performance

The scaling of CMOS technology has continued due to ever increasing demand of greater performance with low power consumption. This demand has grown further by the portable and battery operated devices market. To meet the challenge of greater energy efficiency and performance, a number of power optimization techniques at processor and system components level are proposed by the research community such as clock gating, operand isolation, memory splitting, power gating, dynamic voltage and frequency scaling, etc. This chapter reviews advancements in the dynamic power optimization techniques like clock gating and power gating. This chapter also reviews some architectures and optimization techniques that have been developed for greater power reduction without any significant performance degradation or area cost.

scholarly journals Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1587
Author(s):  
Duo Sheng ◽  
Hsueh-Ru Lin ◽  
Li Tai
Keyword(s):  
High Performance ◽  
Power Reduction ◽  
System On Chip ◽  
Timing Information ◽  
Multi Stage ◽  
Dynamic Voltage ◽  
And Performance ◽  
On Chip ◽  
Maximum Measurement ◽  
Maximum Measurement Error

High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design.

Fuzzy System for DOA Estimation of Coherent Signals

2013 ◽  
Vol 427-429 ◽  
pp. 575-581
Author(s):  
Ya Ling Chen ◽  
Chien Chou Lin
Keyword(s):  
Fuzzy System ◽  
High Performance ◽  
Expert Knowledge ◽  
Doa Estimation ◽  
Coherent Signals ◽  
Fuzzy Logic Systems ◽  
Significant Performance ◽  
And Performance ◽  
Low Sensitivity ◽  
Resolution Estimation

This paper presents an efficient direction-of-arrival (DOA) Estimator for dealing with coherent signals. The empirical results show that significant performance degradation occurs when coherent signals coexist. Therefore, an utilizes the low sensitivity of Bartlett algorithm in estimation of DOAs for coherent signals to yield a low-resolution estimation of DOAs as initial search angle and uses fuzzy logic systems with incorporating expert knowledge to improve the resolution and performance of estimation of DOAs in coherent signals environment. Finally, numerical example was analyzed to illustrate high performance of the proposed method and to confirm the designed procedure.

Power Optimization Techniques for DDR3 SDRAM

2015 ◽  
Author(s):  
Preeti Ranjan Panda ◽  
Vishal Patel ◽  
Praxal Shah ◽  
Namita Sharma ◽  
Vaidyanathan Srinivasan ◽  
...  
Keyword(s):  
Power Optimization ◽  
Optimization Techniques

scholarly journals Design and implementation of CNTFET based ternary 1x1 memories

2019 ◽  
Vol 8 (3) ◽  
pp. 175 ◽  
Author(s):  
S.Tamil Selvan ◽  
M. Sundararajan
Keyword(s):  
High Performance ◽  
Data Access ◽  
Cmos Technology ◽  
Access Time ◽  
The Novel ◽  
Design And Implementation ◽  
Technology Process ◽  
Sram Cell ◽  
And Performance ◽  
Power Application

In this paper presented Design and implementation of CNTFET based Ternary 1x1 RAM memories high-performance digital circuits. CNTFET Ternary 1x1 SRAM memories is implement using 32nm technology process. The CNTFET decresase the diameter and performance matrics like delay,power and power delay, The CNTFET Ternary 6T SRAM cell consists of two cross coupled Ternary inverters one is READ and another WRITE operations of the Ternary 6T SRAM cell are performed with the Tritline using HSPICE and Tanner tools in this tool is performed high accuracy. The novel based work can be used for Low Power Application and Access time is less of compared to the conventional CMOS Technology. The CNTFET Ternary 6T SRAM array module (1X1) in 32nm technology consumes only 0.412mW power and data access time is about 5.23ns.

scholarly journals A Concise Review of Control Techniques for Reliable and Efficient Control of Induction Motor

2018 ◽  
Vol 9 (3) ◽  
pp. 1124
Author(s):  
Abdullah Alwadie
Keyword(s):  
Induction Motor ◽  
Research Work ◽  
Optimization Techniques ◽  
Future Research ◽  
Variable Frequency ◽  
Control Techniques ◽  
Control Scheme ◽  
Control Schemes ◽  
Variable Frequency Drives ◽  
And Performance

<span style="color: black; font-family: 'Times New Roman','serif'; font-size: 10pt; mso-fareast-font-family: SimSun; mso-themecolor: text1; mso-ansi-language: EN-US; mso-fareast-language: EN-US; mso-bidi-language: AR-SA;">Induction motors are work-horse of the industry and major element in energy conversion. The replacement of the existing non-adjustable speed drives with the modern variable frequency drives would save considerable amount of electricity. A proper control scheme for variable frequency drives can enhance the efficiency and performance of the drive. This paper attempt to provide a rigorous review of various control schemes for the induction motor control and provides critical analysis and guidelines for the future research work. A detailed study of sensor based control schemes and sensor-less control schemes has been investigated. The operation, advantages, and limitations of the various control schemes are highlighted and different types of optimization techniques have been suggested to overcome the limitations of control techniques</span>

scholarly journals Preliminary Sailplane Design Using MDO And Multi-Fidelity Analysis

2021 ◽  
Author(s):  
Chris V. Pilcher
Keyword(s):  
Multidisciplinary Design Optimization ◽  
High Performance ◽  
Vortex Lattice ◽  
Optimization Techniques ◽  
Multidisciplinary Design ◽  
Preliminary Design ◽  
Adaptive Meshing ◽  
Analysis Methods ◽  
And Performance ◽  
Modern Optimization

A multidisciplinary design optimization (MDO) strategy for the preliminary design of a sailplane has been developed. The proposed approach applies MDO techniques and multi-fidelity analysis methods which have seen successful use in many aerospace design applications. A customized genetic algorithm (GA) was developed to control the sailplane optimization that included aerodynamics/stability, structures/weights and balance and, performance/airworthiness disciplinary analysis modules. An adaptive meshing routine was developed to allow for accurate modeling of the aero structural couplinginvolved in wing design, which included a finite element method (FEM) structural solver along with a vortex lattice aerodynamics solver. Empirical equations were used to evaluate basic sailplane performance and airworthiness requirements. This research yielded an optimum design that correlated well with an existing high performance sailplane. The results of this thesis suggest that preliminary sailplane design is a well suited application for modern optimization techniques when coupled with, multi-fidelity analysis methods.

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