FPGA Architecture and Design Flow

2021 ◽  
pp. 367-383
Author(s):  
Vaibbhav Taraate
Keyword(s):  
Design Flow ◽  
Fpga Architecture ◽  
Architecture And Design

scholarly journals A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime

2009 ◽  
Vol 2009 ◽  
pp. 1-10 ◽  
Author(s):  
Thilo Pionteck ◽  
Roman Koch ◽  
Carsten Albrecht ◽  
Erik Maehle
Keyword(s):  
System Architecture ◽  
Design Tool ◽  
Design Flow ◽  
Design Tools ◽  
System Architectures ◽  
Flexible System ◽  
Reconfigurable System ◽  
Communication Needs ◽  
On Chip ◽  
Architecture And Design

Runtime reconfigurable system-on-chip designs for FPGAs pose manifold demands on the underlying system architecture and design tool capabilities. The system architecture has to support varying communication needs of a changing number of processing units mapped onto diverse locations. Design tools should support an arbitrary placement of processing modules and the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules. While few works address the design of flexible system architectures, the adjustment of boundaries of reconfigurable regions to the size of the actually instantiated processing modules is hardly ever considered due to design tool limitations. In this paper, a technique for circumventing this restriction is presented. It allows for a rededication of the reconfigurable area to a different number of individually sized reconfigurable regions. This technique is embedded in the design flow of a runtime reconfigurable system architecture for Xilinx Virtex-4 FPGAs. The system architecture will also be presented to provide a realistic application example.

Architecture and Design Flow for a Highly Efficient Structured ASIC

2013 ◽  
Vol 21 (3) ◽  
pp. 424-433 ◽  
Author(s):  
Man-Ho Ho ◽  
Yan-Qing Ai ◽  
Thomas Chun-Pong Chau ◽  
Steve C. L. Yuen ◽  
Chiu-Sing Choy ◽  
...  
Keyword(s):  
Design Flow ◽  
Highly Efficient ◽  
Architecture And Design

HPDP: Architecture and design flow: High performance data processor

2017 ◽  
Author(s):  
Olga Dokianaki ◽  
Volker Baumgarte ◽  
Mohsin Syed ◽  
Constantin Papadas ◽  
Tim Helfers ◽  
...  
Keyword(s):  
High Performance ◽  
Performance Data ◽  
Design Flow ◽  
Data Processor ◽  
Architecture And Design
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