logic bist Latest Research Papers

ASIC Implementation and Analysis of Logic BIST Controller for Ripple Carry Adder at Different Technology

2021 International Conference on Intelligent Technologies (CONIT) ◽

10.1109/conit51480.2021.9498398 ◽

2021 ◽

Author(s):

Shivaprasad Umarani ◽

Meenakshi L Rathod

Keyword(s):

Ripple Carry Adder ◽

Logic Bist

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A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips

IEEE Transactions on Emerging Topics in Computing ◽

10.1109/tetc.2017.2767070 ◽

2020 ◽

Vol 8 (3) ◽

pp. 591-601

Author(s):

Takaaki Kato ◽

Senling Wang ◽

Yasuo Sato ◽

Seiji Kajihara ◽

Xiaoqing Wen

Keyword(s):

Power Control ◽

Control Method ◽

Logic Bist

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Logic BIST With Capture-Per-Clock Hybrid Test Points

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2018.2834441 ◽

2019 ◽

Vol 38 (6) ◽

pp. 1028-1041 ◽

Cited By ~ 5

Author(s):

Elham Moghaddam ◽

Nilanjan Mukherjee ◽

Janusz Rajski ◽

Jedrzej Solecki ◽

Jerzy Tyszer ◽

...

Keyword(s):

Logic Bist ◽

Hybrid Test ◽

Test Points

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Design and Implementation of Power Efficient Logic BIST With High Fault Coverage Using Verilog

2018 International Conference on Networking, Embedded and Wireless Systems (ICNEWS) ◽

10.1109/icnews.2018.8903923 ◽

2018 ◽

Author(s):

K Akhila ◽

N Karuna ◽

Yasha Jyothi M Shirur

Keyword(s):

Fault Coverage ◽

Power Efficient ◽

Design And Implementation ◽

Logic Bist

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Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST

2018 IEEE 27th Asian Test Symposium (ATS) ◽

10.1109/ats.2018.00038 ◽

2018 ◽

Cited By ~ 1

Author(s):

Senling Wang ◽

Tomoki Aono ◽

Yoshinobu Higami ◽

Hiroshi Takahashi ◽

Hiroyuki Iwata ◽

...

Keyword(s):

Fault Detection ◽

Pattern Control ◽

Logic Bist ◽

Degradation Problem

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On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST

2018 IEEE 27th Asian Test Symposium (ATS) ◽

10.1109/ats.2018.00017 ◽

2018 ◽

Author(s):

Shigeyuki Oshima ◽

Takaaki Kato ◽

Senling Wang ◽

Yasuo Sato ◽

Seiji Kajihara

Keyword(s):

Partial Observation ◽

Flip Flop ◽

Scan Test ◽

Logic Bist ◽

Selection For

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XLBIST: X-Tolerant Logic BIST

2018 IEEE International Test Conference (ITC) ◽

10.1109/test.2018.8624738 ◽

2018 ◽

Cited By ~ 2

Author(s):

P. Wohl ◽

J.A. Waicukauski ◽

G.A. Maston ◽

J.E. Colburn

Keyword(s):

Logic Bist

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Design of efficient programmable test-per-scan logic BIST modules

2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS) ◽

10.1109/icmdcs.2017.8211609 ◽

2017 ◽

Author(s):

K. N. Devika ◽

Ramesh Bhakthavatchalu

Keyword(s):

Logic Bist

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Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2016.2572606 ◽

2017 ◽

Vol 25 (1) ◽

pp. 238-246 ◽

Cited By ~ 2

Author(s):

Martin Omana ◽

Daniele Rossi ◽

Filippo Fuzzi ◽

Cecilia Metra ◽

Chandrasekharan Chandra Tirumurti ◽

...

Keyword(s):

Logic Bist

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Programmable MISR modules for logic BIST based VLSI testing

2016 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT) ◽

10.1109/iccicct.2016.7988042 ◽

2016 ◽

Cited By ~ 1

Author(s):

K N Devika ◽

Ramesh Bhakthavatchalu

Keyword(s):

Vlsi Testing ◽

Logic Bist

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logic bist
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

ASIC Implementation and Analysis of Logic BIST Controller for Ripple Carry Adder at Different Technology

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips

Logic BIST With Capture-Per-Clock Hybrid Test Points

Design and Implementation of Power Efficient Logic BIST With High Fault Coverage Using Verilog

Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST

On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST

XLBIST: X-Tolerant Logic BIST

Design of efficient programmable test-per-scan logic BIST modules

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Programmable MISR modules for logic BIST based VLSI testing

Export Citation Format

logic bistRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

ASIC Implementation and Analysis of Logic BIST Controller for Ripple Carry Adder at Different Technology

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips

Logic BIST With Capture-Per-Clock Hybrid Test Points

Design and Implementation of Power Efficient Logic BIST With High Fault Coverage Using Verilog

Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST

On Flip-Flop Selection for Multi-cycle Scan Test with Partial Observation in Logic BIST

XLBIST: X-Tolerant Logic BIST

Design of efficient programmable test-per-scan logic BIST modules

Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST

Programmable MISR modules for logic BIST based VLSI testing

logic bist
Recently Published Documents