Hardware software partitioning using directed acyclic data dependence graph with precedence

n this these we present a system partitioning technique that employs C/C++ as input specification language for hardware/software co-design. The proposed algorithm is able to explore a number of partitioning solutions as compared to other partitioning research. This benefit is obtained by processing data dependency and precedence dependency simultaneously in a new representation called Directed Acyclic Data dependency Graph with Precedence (DADGP). DADGP is an extension of Directed Acyclic Graph (DAG) structure frequently used in the past for partitioning. The DADGP based partitioning algorithm minimizes communication overhead, overall system execution time as well as system cost in terms of hardware area. The algorithm analyzes the DADGP and tries to expose parallelism between processing elements and repeated tasks. The benefits of exposing parallelism with minimum inter PE communication overhead are shown in the experimental results. However, such benefits come with increase in cost due to additional hardware units and their interconnections. DADGP-based partitioning technique is also employed to implement block matching and SOBEL edge detection techniques. Overall, the proposed system partitioning algorithm is fast and powerful enough to handle complicated and large system designs.

Hardware software partitioning using directed acyclic data dependence graph with precedence

n this these we present a system partitioning technique that employs C/C++ as input specification language for hardware/software co-design. The proposed algorithm is able to explore a number of partitioning solutions as compared to other partitioning research. This benefit is obtained by processing data dependency and precedence dependency simultaneously in a new representation called Directed Acyclic Data dependency Graph with Precedence (DADGP). DADGP is an extension of Directed Acyclic Graph (DAG) structure frequently used in the past for partitioning. The DADGP based partitioning algorithm minimizes communication overhead, overall system execution time as well as system cost in terms of hardware area. The algorithm analyzes the DADGP and tries to expose parallelism between processing elements and repeated tasks. The benefits of exposing parallelism with minimum inter PE communication overhead are shown in the experimental results. However, such benefits come with increase in cost due to additional hardware units and their interconnections. DADGP-based partitioning technique is also employed to implement block matching and SOBEL edge detection techniques. Overall, the proposed system partitioning algorithm is fast and powerful enough to handle complicated and large system designs.

Secondary and Tertiary Voltage Control of a Multi-Region Power System

This paper presents techniques for the application of tertiary and secondary voltage control through the use of intelligent proportional integral derivative (PID) controllers and the wide area measurement system (WAMS) in the IEEE 39 bus system (New England system). The paper includes power system partitioning, pilot bus selection, phasor measurement unit (PMU) placement, and optimal secondary voltage control parameter calculations to enable the application of the proposed voltage control. The power system simulation and analyses were performed using the DIgSILENT and MATLAB software applications. The optimal PMU placement was performed in order to apply secondary voltage control. The tertiary voltage control was performed through an optimal power flow optimization process in order to minimize the active power losses. Two different methods were used to design the PID secondary voltage control, namely, genetic algorithm (GA) and neural network based on genetic algorithm (NNGA). A comparison of system performances using these two methods under different operating conditions is presented. The results show that NNGA secondary PID controllers are more robust than GA ones. The paper also presents a comparison between system performance with and without secondary voltage control, in terms of voltage deviation index and total active power losses. The graph theory is used in system partitioning, and sensitivity analysis is used in pilot bus selection, the results of which proved their effectiveness.

Spatial control over near-critical-point operation ensures fidelity of ParABS-mediated bacterial genome segregation

ABSTRACTIn bacteria, most low-copy-number plasmid and chromosomally encoded partition systems belong to the tripartite ParABS partition machinery. Despite the importance in genetic inheritance, the mechanisms of ParABS-mediated genome partition are not well understood. Combining theory and experiment, we provided evidences that the ParABS system – partitioning via the ParA gradient-based Brownian ratcheting – operates near a critical point in vivo. This near-critical-point operation adapts the segregation distance of replicated plasmids to the half-length of the elongating nucleoid, ensuring both cell halves to inherit one copy of the plasmids. Further, we demonstrated that the plasmid localizes the cytoplasmic ParA to buffer the partition fidelity against the large cell-to-cell fluctuations in ParA level. Thus, the spatial control over the near-critical-point operation not only ensures both sensitive adaption and robust execution of partitioning, but sheds light on the fundamental question in cell biology: How do cells faithfully measure cellular-scale distance by only using molecular-scale interactions?