ViTaL: Verifying Trojan-Free Physical Layouts through Hardware Reverse Engineering

The semiconductor industry is heavily relying on outsourcing of design, fabrication, and testing to third parties. The threat of possibly malicious actors in this ramified supply-chain poses a risk for the integrity of integrated circuits (ICs) and hardware Trojans (HTs) are a heavily discussed topic in academia and the industry. A variety of pre- and post-silicon HT prevention and detection techniques has been suggested in prior works. Hardware reverse engineering has the potential to detect potential modification in physical layouts. Yet, there is no model to qualitatively and quantitatively rate the complex and expensive reverse engineering (RE) process addressing its inherent process aberrations and consequently provide a tool for layout verification. The ViTaL framework introduces a statistical validation technique, based on physical layout verification through RE and considers all potential sources of errors. The golden-model based framework is technology-agnostic, scaleable, and user input is optional. For the first time, results of fine pitch metallization layers of a CMOS 40nm process node IC are presented quantitatively and the limitations and possibilities are discussed.<br>

ViTaL: Verifying Trojan-Free Physical Layouts through Hardware Reverse Engineering

The semiconductor industry is heavily relying on outsourcing of design, fabrication, and testing to third parties. The threat of possibly malicious actors in this ramified supply-chain poses a risk for the integrity of integrated circuits (ICs) and hardware Trojans (HTs) are a heavily discussed topic in academia and the industry. A variety of pre- and post-silicon HT prevention and detection techniques has been suggested in prior works. Hardware reverse engineering has the potential to detect potential modification in physical layouts. Yet, there is no model to qualitatively and quantitatively rate the complex and expensive reverse engineering (RE) process addressing its inherent process aberrations and consequently provide a tool for layout verification. The ViTaL framework introduces a statistical validation technique, based on physical layout verification through RE and considers all potential sources of errors. The golden-model based framework is technology-agnostic, scaleable, and user input is optional. For the first time, results of fine pitch metallization layers of a CMOS 40nm process node IC are presented quantitatively and the limitations and possibilities are discussed.<br>

Enhanced Processability and Thermal Fatigue Reliability With Low Melting Point SnBi Solder Alloy LMPA-Q

SnBi based solder alloys become an interesting alternative for standard SnAgCu as they can be used to solder components at much lower temperature. The typically 50°C lower solder reflow temperature is less damaging for PCB and components, and also prevents hot tear and head-in-pillow failures for large fine pitch BGA components. A reasonable concern for these low-melting temperature solders is the thermal cycling reliability performance, in particular for harsh conditions such as automotive products. In this work, thermal cycling testing and failure analysis have been performed on 9 × 9 mm size QFN components and large chip components (2010 and 2512) which are typically sensitive to thermal fatigue. The results are benchmarked to standard SAC alloy. Also the process advantages from the low temperature solder alloys are depicted in this paper. Finally, the effect of Pb contamination on this SnBi based solder is investigated.

The Effect of an Ag Nanofilm on Low-Temperature Cu/Ag-Ag/Cu Chip Bonding in Air

Low-temperature Cu-Cu bonding technology plays a key role in high-density and high-performance 3D interconnects. Despite the advantages of good electrical and thermal conductivity and the potential for fine pitch patterns, Cu bonding is vulnerable to oxidation and the high temperature of the bonding process. In this study, chip-level Cu bonding using an Ag nanofilm at 150 °C and 180 °C was studied in air, and the effect of the Ag nanofilm was investigated. A 15-nm Ag nanofilm prevented Cu oxidation prior to the Cu bonding process in air. In the bonding process, Cu diffused rapidly to the bonding interface and pure Cu-Cu bonding occurred. However, some Ag was observed at the bonding interface due to the short bonding time of 30 min in the absence of annealing. The shear strength of the Cu/Ag-Ag/Cu bonding interface was measured to be about 23.27 MPa, with some Ag remaining at the interface. This study demonstrated the good bonding quality of Cu bonding using an Ag nanofilm at 150 °C.