The L∞ Hausdorff Voronoi Diagram Revisited

We revisit the [Formula: see text] Hausdorff Voronoi diagram of clusters of points in the plane and present a simple two-pass plane sweep algorithm to construct it. This problem is motivated by applications in the semiconductor industry, in particular, critical area analysis and yield prediction in VLSI design. We show that the structural complexity of this diagram is [Formula: see text], where [Formula: see text] is the number of given clusters and [Formula: see text] is a number of specially crossing clusters, called essential. Our algorithm runs in [Formula: see text] time and [Formula: see text] space, where [Formula: see text] reflects a slight superset of essential crossings, [Formula: see text], and [Formula: see text] is the total number of crossing clusters. For non-crossing clusters ([Formula: see text]) or clusters with only a small number of crossings ([Formula: see text]) the algorithm is optimal. The latter is the case of interest in the motivating application, where [Formula: see text]. This is achieved by augmenting the wavefront data structure of the plane sweep, and a preprocessing step, based on point dominance, which is interesting in its own right.

THE HAUSDORFF VORONOI DIAGRAM OF POLYGONAL OBJECTS: A DIVIDE AND CONQUER APPROACH

We study the Hausdorff Voronoi diagram of a set S of polygonal objects in the plane, a generalization of Voronoi diagrams based on the maximum distance of a point from a polygon, and show that it is equivalent to the Voronoi diagram of S under the Hausdorff distance function. We investigate the structural and combinatorial properties of the Hausdorff Voronoi diagram and give a divide and conquer algorithm for the construction of this diagram that improves upon previous results. As a byproduct we introduce the Hausdorff hull, a structure that relates to the Hausdorff Voronoi diagram in the same way as a convex hull relates to the ordinary Voronoi diagram. The Hausdorff Voronoi diagram finds direct application in the problem of computing the critical area of a VLSI Layout, a measure reflecting the sensitivity of a VLSI design to random manufacturing defects, described in a companion paper.13