FPGA-based switch-level fault emulation using modular-based dynamic partial reconfiguration

Fault simulation is a process of purposely injecting faults into a target circuit and observing a circuit's behavior in the presence of faulty logic. This observation helps designers to implement certain fault tolerance schemes thereby combating hardware failures. Fault simulation in most implementations has until now been software-based. Several fault emulation approaches have been proposed to accelerate fault simulation process using FPGA. There are generally two types of hardware fault injection: injector-based and reconfiguration-based. Injector-based methods require inserting fault injector circuitry into the circuit under test thus adding hardware overhead. On the other hand, reconfigurable-based methods require much less hardware overhead. However, these methods may be very slow because reconfiguring an entire FPGA device can take several seconds. This long confirmation time is usually the bottleneck of the emulation system. This project proposes a novel switch-level fault emulation system utilizing FPGA modular-based dynamic partial reconfiguration (DPR). In the proposed approach, faults are modeled at switch-level for an accurate fault list and mapped to gate-level for efficient synthesis. In addition, circuit-under-test is partitioned using an unbalanced tree structure to facilitate modular-based DPR. Modular-based DPR partitions a design into modules, and each module can be reconfigured independently without shutting down the FPGA. This capability is applied to fault injection where each circuit partition can be reconfigured individually without erasing the rest of FPGA. First a partial configuration bitstream representing the faulty partition is created. Fault injection can then be performed by downloading only this partial bitstream to FPGA, thereby eliminating the need for full-device reconfiguration and therefore reducing fault emulation runtime. This report presents both a theoretical explanation and the implementation details regarding this approach. Experimental results are also be provided. [sic]

FPGA-based switch-level fault emulation using modular-based dynamic partial reconfiguration

Fault simulation is a process of purposely injecting faults into a target circuit and observing a circuit's behavior in the presence of faulty logic. This observation helps designers to implement certain fault tolerance schemes thereby combating hardware failures. Fault simulation in most implementations has until now been software-based. Several fault emulation approaches have been proposed to accelerate fault simulation process using FPGA. There are generally two types of hardware fault injection: injector-based and reconfiguration-based. Injector-based methods require inserting fault injector circuitry into the circuit under test thus adding hardware overhead. On the other hand, reconfigurable-based methods require much less hardware overhead. However, these methods may be very slow because reconfiguring an entire FPGA device can take several seconds. This long confirmation time is usually the bottleneck of the emulation system. This project proposes a novel switch-level fault emulation system utilizing FPGA modular-based dynamic partial reconfiguration (DPR). In the proposed approach, faults are modeled at switch-level for an accurate fault list and mapped to gate-level for efficient synthesis. In addition, circuit-under-test is partitioned using an unbalanced tree structure to facilitate modular-based DPR. Modular-based DPR partitions a design into modules, and each module can be reconfigured independently without shutting down the FPGA. This capability is applied to fault injection where each circuit partition can be reconfigured individually without erasing the rest of FPGA. First a partial configuration bitstream representing the faulty partition is created. Fault injection can then be performed by downloading only this partial bitstream to FPGA, thereby eliminating the need for full-device reconfiguration and therefore reducing fault emulation runtime. This report presents both a theoretical explanation and the implementation details regarding this approach. Experimental results are also be provided. [sic]