An Improved Parallel FFT Algorithm Based on the GPU

With the extensive applications of FFT in digital signal processing and image signal processing which needs a extensive application of large-scale computing, it become more and more important to improve parallelism, especially efficient and scalable parallel of FFT algorithm. This paper improves the parallelism of the FFT algorithm based on the Six-Step FFT algorithm. The introduction of GPU to parallel computing is to realize parallel FFT computing in a single machine and to improve the speed of Frontier transform. With the optimization strategy of the mapping hiding the transport matrix, the performance of parallel FFT algorithm after optimization is remarkably promoted by the assignment of matrix calculation and butterfly computation to GPU. Finally it applies to design the digital filter in seismic data.

PARALLEL FFT ALGORITHMS ON NETWORK-ON-CHIPS

This paper presents parallel FFT algorithms with different degree of computation and communication overheads for multiprocessors in a Network-on-Chip (NoC) environment. Of the three parallel FFT algorithms presented in this paper, we propose two parallel FFT algorithms for a 2D NoC that can contain a variable number of processing elements (PEs) and one is a reference parallel FFT algorithm for comparison. A parallel FFT algorithm we propose increases performance by assigning well-balanced computation tasks to PEs. The execution times are reduced because the algorithm uses data locality well to avoid unnecessary data exchanges among PEs and removes the overall idle periods by2 a balanced task scheduling. An enhanced version of this algorithm is suggested in which communication traffic is reduced. In this algorithm, returning transformed data to an original PE after one computation stage before sending them to a next PE for the following stage is removed. Instead, we propose a method that enables to keep regularity of the data communication and computations with twiddle factors. According to the simulation result from our cycle-accurate SystemC NoC model with a parametrizable 2-D mesh architecture, and the analysis of the algorithms in time and complexity, our proposed algorithms are shown to outperform the reference parallel FFT algorithm and FFT implementations on TI Digital Signal Processors (DSPs) that have similar specifications to our simulation environment.

FFT for the APE Parallel Computer

We present a parallel FFT algorithm for SIMD systems following the "Transpose Algorithm" approach. The method is based on the assignment of the data field onto a one-dimensional ring of systolic cells. The systolic array can be universally mapped onto any parallel system. In particular for systems with next-neighbor connectivity our method has the potential to improve the efficiency of matrix transposition by use of hyper-systolic communication. We have realized a scalable parallel FFT on the APE100/Quadrics massively parallel computer, where our implementation is part of a two-dimensional hydrodynamics code for turbulence studies.