DSP TMS320C6678 Based SHVC Encoder Implementation and its Optimization

The programmable processors newest technologies, as for example the multicore Digital Signal Processors (DSP), offer a promising solution for overcoming the complexity of the real time video encoding application. In this paper, the SHVC video encoder was effectively implemented just on a single core among the eight cores of TMS320C6678 DSP for a Common Intermediate Format (CIF)input video sequence resolution(352x288). Performance optimization of the SHVC encoder had reached up 41% compared to its reference software enabling a real-time implementation of the SHVC encoder for CIF input videos sequence resolution. The proposed SHVC implementation was carried out on different quantization parameters (QP). Several experimental tests had proved our performance achievement for real-time encoding on TMS320C6678.

Modal analysis and demonstration of metastructure combining local resonators and an autonomous synchronized switch damping circuit

A locally resonant metastructure is a promising approach for low-frequency vibration attenuation, whereas the attachment of many resonators results in unnecessary and multiple resonance outside the bandgap. To address this issue, we propose a damping metastructure combining local resonators and an autonomous synchronized switch damping circuit. On the basis of modal analysis, we derive an electromechanically coupled equation of the proposed metastructure. The piezo ceramics, which are attached on a small portion of the metastructure and connected to the circuit, remarkably decrease the magnitude of the resonant vibration with no extra sensors, signal processors, or power sources. The displacement at unnecessary resonance was decreased by approximately 75%. The results of the coupled analysis were similar to the experimentally observed results in terms of the location and width of the bandgap on the frequency axis and the decreased displacement for the circuit. The proposed technique can overcome the disadvantage of the metastructure.

High temperature molecular-based phase transition compounds with tunable and switchable dielectric properties

Molecular-based dielectric switching materials have recently attracted tremendous interest in the fields of data storage, signal processors and snesors due to tunability, flexibility and good biocompatibility, which is promissing for...

Implementation of PI and MPC-Based Speed Controllers for a Drive with Elastic Coupling on a PLC Controller

This paper presents some of the issues related to the implementation of advanced control structures (PI controller with additional feedback, Model Predictive Controller) for drives with elastic coupling on a programmable logic controller (PLC). The predominant solutions to electric drive control include the use of rapid prototyping cards, signal processors or programmable matrices. Originally, PLC controllers were used to automate sequential processes, but for several years now, a trend related to their implementation for advanced control objects can be observed. This is mainly due to their compact design, immunity to disturbances and standard programming languages. The following chapters of the paper present the mathematical model of the drive and describe the implementation of the proposed control structures. A PI controller with additional feedback loops and a predictive controller are taken into consideration. Their impact on the CPU load was analysed, and the work was summarised by a comprehensive experimental study. The presented results confirm that it is possible to implement advanced control structures on a PLC controller for drives with elastic coupling while maintaining a sufficiently low load on its CPU.

Counter-Interception and Counter-Exploitation Features of Noise Radar Technology

In defense applications, the main features of radars are the Low Probability of Intercept (LPI) and the Low Probability of Exploitation (LPE). The counterpart uses more and more capable intercept receivers and signal processors thanks to the ongoing technological progress. Noise Radar Technology (NRT) is probably a very effective answer to the increasing demand for operational LPI/LPE radars. The design and selection of the radiated waveforms, while respecting the prescribed spectrum occupancy, has to comply with the contrasting requirements of LPI/LPE and of a favorable shape of the ambiguity function. Information theory seems to be a “technologically agnostic” tool to attempt to quantify the LPI/LPE capability of noise waveforms with little, or absent, a priori knowledge of the means and the strategies used by the counterpart. An information theoretical analysis can lead to practical results in the design and selection of NRT waveforms.

Enhanced and Efficient Carry Select Adder with Minimal Delay

In today’s digital world, Arithmetic computations have been evolved as a core factor in digital signal processors, micro-controllers, and systems using arithmetic and logical operations such as adders, multipliers, image processors, and signal processors. One of the elements that play an important role in performing arithmetic calculations is an adder. Among many adders, the Carry Select Adder produces less propagation delay. However, there may be an increased delay, power consumption, and area required in the case of a normal Carry Select Adder. To overcome the mentioned drawbacks, an improved model of Carry Select Adder has been designed that uses Binary to Excess – 1 Converter. Instead of using multiple blocks of Ripple Carry Adders (RCAs), it is efficient and effective if one of the blocks is replaced with Binary to Excess – 1 Converter. As a result, we can achieve a high speed adder with minimal delay, minimal power, and reduced area.

Simulation and Analysis of different CMOS Full Adders for Delay Optimisation

Full adder circuit is one among the fundamental and necessary digital part. The full adder is be a part of microprocessors, digital signal processors etc. It's needed for the arithmetic and logical operations. Full adder design enhancements are necessary for recent advancement. The requirement of an adder cell is to provide high speed, consume low power and provide high voltage swing. This paper analyses and compares 3 adders with completely different logic designs (Conventional, transmission gate & pseudo NMOS) for transistor count, power dissipation and delay. The simulation is performed in Cadence virtuoso tool with accessible GPDK – 180nm kit. Transmission gate full adder has sheer advantage of high speed, fewer space and also it shows higher performance in terms of delay. Keywords: Delay, power dissipation, voltage, transistor sizing.