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2012 Symposium on VLSI Technology (VLSIT)
Latest Publications
TOTAL DOCUMENTS
97
(FIVE YEARS 0)
H-INDEX
20
(FIVE YEARS 0)
Published By IEEE
9781467308465, 9781467308472
Latest Documents
Most Cited Documents
Contributed Authors
Related Sources
Related Keywords
Latest Documents
Most Cited Documents
Contributed Authors
Related Sources
Related Keywords
Thermal stress characteristics and impact on device keep-out zone for 3-D ICs containing through-silicon-vias
2012 Symposium on VLSI Technology (VLSIT)
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10.1109/vlsit.2012.6242482
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2012
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Cited By ~ 1
Author(s):
Tengfei Jiang
◽
Suk-Kyu Ryu
◽
Qiu Zhao
◽
Jay Im
◽
Ho-Young Son
◽
...
Keyword(s):
Thermal Stress
◽
Through Silicon Vias
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Silicon Vias
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Implementing cubic-phase HfO2 with κ-value ∼ 30 in low-VT replacement gate pMOS devices for improved EOT-Scaling and reliability
2012 Symposium on VLSI Technology (VLSIT)
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10.1109/vlsit.2012.6242444
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2012
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Cited By ~ 6
Author(s):
Lars-Ake Ragnarsson
◽
Christoph Adelmann
◽
Yuichi Higuchi
◽
Karl Opsomer
◽
Anabela Veloso
◽
...
Keyword(s):
Cubic Phase
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Dynamic ‘hour glass’ model for SET and RESET in HfO2 RRAM
2012 Symposium on VLSI Technology (VLSIT)
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10.1109/vlsit.2012.6242468
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2012
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Cited By ~ 22
Author(s):
R. Degraeve
◽
A. Fantini
◽
S. Clima
◽
B. Govoreanu
◽
L. Goux
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...
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Recent progress and challenges for relay logic switch technology
2012 Symposium on VLSI Technology (VLSIT)
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10.1109/vlsit.2012.6242452
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2012
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Cited By ~ 5
Author(s):
Tsu-Jae King Liu
◽
Louis Hutin
◽
I-Ru Chen
◽
Rhesa Nathanael
◽
Yenhao Chen
◽
...
Keyword(s):
Recent Progress
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Demonstration of inter-chip data transmission in a three-dimensional stacked chip fabricated by chip-level TSV integration
2012 Symposium on VLSI Technology (VLSIT)
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10.1109/vlsit.2012.6242518
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2012
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Cited By ~ 4
Author(s):
Kazuyuki Hozawa
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Futoshi Furuta
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Yuko Hanaoka
◽
Mayu Aoki
◽
Kenichi Osada
◽
...
Keyword(s):
Data Transmission
◽
Three Dimensional
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Chip Data
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Hybrid memory cube new DRAM architecture increases density and performance
2012 Symposium on VLSI Technology (VLSIT)
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10.1109/vlsit.2012.6242474
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2012
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Cited By ~ 226
Author(s):
Joe Jeddeloh
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Brent Keeth
Keyword(s):
Hybrid Memory
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And Performance
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Development of ultra-thin Chip-on-Wafer process using bumpless interconnects for three-dimensional memory/logic applications
2012 Symposium on VLSI Technology (VLSIT)
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10.1109/vlsit.2012.6242516
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2012
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Cited By ~ 2
Author(s):
N. Maeda
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H. Kitada
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K. Fujimoto
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Y. S. Kim
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S. Kodama
◽
...
Keyword(s):
Three Dimensional
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InGaSb: Single channel solution for realizing III–V CMOS
2012 Symposium on VLSI Technology (VLSIT)
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10.1109/vlsit.2012.6242523
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2012
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Cited By ~ 10
Author(s):
Z. Yuan
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A. Nainani
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A. Kumar
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X. Guan
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B. R. Bennett
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...
Keyword(s):
Single Channel
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Steep-slope tunnel field-effect transistors using III–V nanowire/Si heterojunction
2012 Symposium on VLSI Technology (VLSIT)
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10.1109/vlsit.2012.6242454
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2012
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Cited By ~ 90
Author(s):
Katsuhiro Tomioka
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Masatoshi Yoshimura
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Takashi Fukui
Keyword(s):
Field Effect
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Field Effect Transistors
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Steep Slope
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Sub-fM DNA sensitivity by self-aligned maskless thin-film transistor-based SoC bioelectronics
2012 Symposium on VLSI Technology (VLSIT)
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10.1109/vlsit.2012.6242494
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2012
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Cited By ~ 1
Author(s):
Min-Cheng Chen
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Chang-Hsien Lin
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Chia-Yi Lin
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Fu-Kuo Hsueh
◽
Wen-Hsien Huang
◽
...
Keyword(s):
Thin Film
◽
Thin Film Transistor
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