Sixth Annual IEEE International ASIC Conference and Exhibit
Latest Publications

TOTAL DOCUMENTS

117

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0780313755

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

XBERT - A versatile 622 Mb/sec bit error rate generator/receiver methodology for SONET OC-3 application

Sixth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1993.410738 ◽

2002 ◽

Author(s):

P.K. Sun ◽

G. Lowe

Keyword(s):

Bit Error Rate ◽

Error Rate

A baseband mixed signal ASIC for CDMA subscriber equipment applications

Sixth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1993.410799 ◽

2002 ◽

Cited By ~ 1

Author(s):

M. Nettles ◽

C. Robert ◽

A. Weiland ◽

C.E. Wheatley ◽

I. McKay ◽

...

Keyword(s):

Mixed Signal

System level verification of ASIC chip-sets

Sixth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1993.410723 ◽

2002 ◽

Author(s):

S. Tayal ◽

A. Moezzi ◽

E. Magnusson

Keyword(s):

System Level ◽

Asic Chip

An ASIC signal processor for electronic warfare receivers

Sixth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1993.410709 ◽

2002 ◽

Cited By ~ 1

Author(s):

G. MacKean ◽

R. Inkol

Keyword(s):

Electronic Warfare ◽

Signal Processor

Analysis of the gap between behavioral and gate level fault simulation

Sixth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1993.410827 ◽

2002 ◽

Cited By ~ 2

Author(s):

C.-I.H. Chen ◽

S. Perumal

Keyword(s):

Fault Simulation

High-level DSP synthesis using the COMET design system

Sixth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1993.410748 ◽

2002 ◽

Author(s):

Ching-Tang Chang ◽

K. Rose ◽

R.A. Walker

Keyword(s):

Design System ◽

High Level

ECHO2, a multi-channel, single-chip, VLSI ECHO canceller with embedded TMS320C10 DSP

Sixth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1993.410818 ◽

2002 ◽

Author(s):

D. Prysby ◽

R. Younce ◽

J. Duhachek ◽

D. Baughman

Keyword(s):

Single Chip ◽

Echo Canceller

A CMOS circuit technique for high-speed RAMs

Sixth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1993.410715 ◽

2002 ◽

Cited By ~ 5

Author(s):

J. Alowersson

Keyword(s):

High Speed ◽

Cmos Circuit ◽

Circuit Technique

A transistor voltage reference-and what the bandgap has to do with it

Sixth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1993.410796 ◽

2002 ◽

Author(s):

A. Brokaw

Keyword(s):

Voltage Reference ◽

Transistor Voltage

Design verification techniques for system level testing using ASIC level BIST implementations

Sixth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1993.410826 ◽

2002 ◽

Cited By ~ 6

Author(s):

C.E. Stroud ◽

Gang Liang

Keyword(s):

System Level ◽

Design Verification ◽

Verification Techniques

Sixth Annual IEEE International ASIC Conference and ExhibitLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

XBERT - A versatile 622 Mb/sec bit error rate generator/receiver methodology for SONET OC-3 application

A baseband mixed signal ASIC for CDMA subscriber equipment applications

System level verification of ASIC chip-sets

An ASIC signal processor for electronic warfare receivers

Analysis of the gap between behavioral and gate level fault simulation

High-level DSP synthesis using the COMET design system

ECHO2, a multi-channel, single-chip, VLSI ECHO canceller with embedded TMS320C10 DSP

A CMOS circuit technique for high-speed RAMs

A transistor voltage reference-and what the bandgap has to do with it

Design verification techniques for system level testing using ASIC level BIST implementations

Sixth Annual IEEE International ASIC Conference and Exhibit
Latest Publications