Stray radiation produced in FLASH electron beams characterized by the MiniPIX Timepix3 Flex detector

This work aims to characterize ultra-high dose rate pulses (UHDpulse) electron beams using the hybrid semiconductor pixel detector. The Timepix3 (TPX3) ASIC chip was used to measure the composition, spatial, time, and spectral characteristics of the secondary radiation fields from pulsed 15–23 MeV electron beams. The challenge is to develop a single compact detector that could extract spectrometric and dosimetric information on such high flux short-pulsed fields. For secondary beam measurements, PMMA plates of 1 and 8 cm thickness were placed in front of the electron beam, with a pulse duration of 3.5 µs. Timepix3 detectors with silicon sensors of 100 and 500 µm thickness were placed on a shifting stage allowing for data acquisition at various lateral positions to the beam axis. The use of the detector in FLEXI configuration enables suitable measurements in-situ and minimal self-shielding. Preliminary results highlight both the technique and the detector’s ability to measure individual UHDpulses of electron beams delivered in short pulses. In addition, the use of the two signal chains per-pixel enables the estimation of particle flux and the scattered dose rates (DRs) at various distances from the beam core, in mixed radiation fields.

Design of a BIST implemented AES crypto-processor ASIC

This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.

Miniaturized On-Chip NFC Antenna versus Screen-Printed Antenna for the Flexible Disposable Sensor Strips

With the ongoing trend toward miniaturization via system-on-chip (SoC), both radio-frequency (RF) SoCs and on-chip multi-sensory systems are gaining significance. This paper compares the inductance of a miniaturized on-chip near field communication (NFC) antenna versus the conventional screen-printed on-substrate ones that have been used for the transfer of sensory data from a chip to a cell phone reader. Furthermore, the transferred power efficiency in a coupled NFC system is calculated for various chip coil geometries and the results are compared. The proposed NFC antenna was fabricated via a lithography process for an application-specific integrated circuit (ASIC) chip. The chip had a small area of 2.4 × 2.4 mm2, therefore a miniaturized NFC antenna was designed, whereas the screen-printed on-substrate antennas had an area of 35 × 51 mm2. This paper investigates the effects of different parameters such as conductor thickness and materials, double layering, and employing ferrite layers with different thicknesses on the performance of the on-chip antennas using full-wave simulations. The presence of a ferrite layer to increase the inductance of the antenna and mitigate the interactions with backplates has proven useful. The best performance was obtained via double-layering of the coils, which was similar to on-substrate antennas, while a size reduction of 99.68% was gained. Consequently, the coupling factors and maximum achievable power transmission efficiency of the on-chip antenna and on-substrate antenna were studied and compared.

One-chip analog circuits for a new type of plasma wave receiver on board space missions

Plasma waves are important observational targets for scientific missions investigating space plasma phenomena. Conventional fast Fourier transform (FFT)-based spectrum plasma wave receivers have the disadvantages of a large size and a narrow dynamic range. This paper proposes a new type of FFT-based spectrum plasma wave receiver that overcomes the disadvantages of conventional receivers. The receiver measures and calculates the whole spectrum by dividing the observation frequency range into three bands: bands 1, 2, and 3, which span 1 Hz to 1 kHz, 1 to 10 kHz, and 10 to 100 kHz, respectively. To reduce the size of the receiver, its analog section was realized using application-specific integrated circuit (ASIC) technology, and an ASIC chip was successfully developed. The dimensions of the analog circuits were 4.21 mm × 1.16 mm. To confirm the performance of the ASIC, a test system for the receiver was developed using the ASIC, an analog-to-digital converter, and a personal computer. The frequency resolutions for bands 1, 2, and 3 were 3.2, 32, and 320 Hz, respectively, and the average time resolution was 384 ms. These frequency and time resolutions are superior to those of conventional FFT-based receivers.

One-chip analogue circuits for a new type of plasma wave receiver onboard space missions

Plasma waves are important observational targets for scientific missions investigating space plasma phenomena. Conventional fast Fourier transform (FFT)-based spectrum plasma wave receivers have the disadvantages of a large size and a narrow dynamic range. This paper proposes a new type of FFT-based spectrum plasma wave receiver that overcomes the disadvantages of conventional receivers. The receiver measures and calculates the whole spectrum by dividing the observation frequency range into three bands: bands 1, 2, and 3, which span 1 Hz to 1 kHz, 1 to 10 kHz, and 10 to 100 kHz, respectively. To reduce the size of the receiver, its analog section was realized using application-specific integrated circuit (ASIC) technology, and an ASIC chip was successfully developed. The dimensions of the analog circuits were 4.21 mm x 1.16 mm. To confirm the performance of the ASIC, a test system for the receiver was developed using the ASIC, an analog-to-digital converter, and a personal computer. The frequency resolutions for bands 1, 2, and 3 were 3.2, 32, and 320 Hz respectively, and the average time resolution was 384 ms. These frequency and time resolutions are superior to those of conventional FFT-based receivers.