Design and Power Dissipation Consideration of PFAL CMOS v/s Conventional CMOS based 2:1 Multiplexer and Full Adder

Increasing transistor switching time and rising count of transistors integrated over a chip area has given a high pace in computing systems by several orders of magnitude. With the integration of circuits, number of gates and transistors are increasing per chip area. CMOS Logic family is preferred due to its performance and impeccable noise margins over other families. However with integration in every digital circuit, the energy due to switching of gate doesn’t decrease at same rate as gates are increased per chip area. Due to this, power dissipation becomes significant and also reduction of heat becomes more complicated and expensive. In CMOS based circuits dynamic power requirement is becoming major concern in digital circuits. In this paper, the work is focused on reducing the power dissipation in circuits which is increasing with down scaling of circuits. The work is done on 2:1 multiplexer and full adder circuit. Adiabatic logic with positive feedback (PFAL) is applied to redesign the circuit with input power taken as sinusoidal source of 3.3 V and analysis is done for power dissipation between conventional CMOS and PFAL based CMOS circuits. In comparison with the conventional CMOS 2:1 multiplexer circuit, the designed PFAL CMOS 2:1 multiplexer circuit has less power dissipation as 80.871 picoWatts while conventional CMOS circuit has 6.9090 nanoWatts with the same behavior of circuit. Also for full adder conventional CMOS circuit have 48.0452 picoWatts while PFAL based full adder has 3.9089 picoWatts.

Analysis of circuit performance of Ge-Si hetero structure TFET based on analytical model

Purpose High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit. Design/methodology/approach Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances. Findings The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter. Originality/value Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

Investigation on Power, Delay and Area optimization of XOR Gate

Nowadays a mobile computing and multimedia applications are need for high-performance reduced size and low-power devices. The multiplication is major operation in any signal processing applications. In any multiplier architecture, adder is one of the major processing elements. In which XOR is the basic block of an adder and multiplier. In this paper, a various design styles of XOR Gate have been surveyed and simulated using Microwind tool. In that XOR gate was analyzed the power using the different styles. They are conventional XOR gate, Pass transistor logic based EX-OR gate, Static inverter based EX-OR gate, Transmission Gate based EX-OR Gate, EX-OR Gate based on 8 & 6 Transistor & and Modified version of EX-OR Gate The CMOS circuit layout was created and simulated in Microwind software. In that the proposed XOR-based circuit has 40.17% of power consumption has improved &14.28 % of area in-terms of number of transistor improved as compare to modified version of EX-OR Gate design.