Design of a multi-function high-speed digital baseband data acquisition system

A multi-function digital baseband data acquisition system is designed for the sampling, distribution and recording of wide-band multi-channel astronomical signals. The system hires a SNAP2 board as a digital baseband converter to digitize, channelize and packetize the received signal. It can be configured dynamically from a single channel to eight channels with a maximum bandwidth of 4096 MHz. Eight parallel HASHPIPE instances run on four servers, each carrying two NVMe SSD cards, achieving a total continuous write rate of 8 GB s−1. Data are recorded in the standard VDIF file format. The system is deployed on a 25-meter radio telescope to verify its functionality based on pulsar observations. Our results indicate that during the 30-minute observation period, the system achieved zero data loss at a data recording rate of 1 GB s−1 on a single server. The system will serve as a verification platform for testing the functions of the QTT (QiTai radio Telescope) digital backend system. In addition, it can be used as a baseband/VLBI (Very Long Baseline Interferometry) recorder or D-F-engine of correlator/beamformer as well.

Design of a Digital Baseband Processor for UHF Tags

In this paper, we present a new digital baseband processor for UHF tags. It is a low-power and low-voltage digital circuit and adopts the Chinese military standard protocol GJB7377.1. The processor receives data or commands from the RF front-end and carries out various functions, such as receiving and writing data to memory, reading and sending memory data to the RF front-end and killing tags. The processor consists of thirteen main sub-modules: TPP decoding, clock management, random number generator, power management, memory controller, cyclic redundancy check, FM0 encoding, input data processing, output data processing, command detection module, initialization module, state machine module and controller. We use ModelSim for the TPP decoding simulation and communication simulation between tag and reader, and the simulation results meet the design requirements. The processor can be applied to UHF tags and has been taped out using a TSMC 0.18 um CMOS process.