Improved Design of a 4-bit Absolute-Value Detector Using Simplified Chain Carry Adder

4-bit absolute-value detector (AVD), as one of the basic implementations of bit arithmetic with logic circuits, can help grab a better understanding about digital integrated circuits. Conventional 4-bit AVDs scheme in a multi-comparator and multiplexers, or need to consider multiple situations of overflow and carry-in, both of which could make the final circuit to be complex, labyrinthine and inefficient in the meantime. In this paper, a new design of 4-bit AVD is proposed, the topology of which includes a 2’s complement calculator and a specially designed logic circuit known as chain carry adder (CCA). The whole circuit is concise and the critical path is rigorously considered to make it as short as possible. The delay is set to 1.5 times its minimum, which is positively corresponding to the length of the critical path, the energy accordingly reaches its lower limit. Gate sizing and Device Voltage (VDD) optimization are proceeded for the exact purpose of proving that the circuit energy is minimized.

Double Power Supplies and Cross-zero Clocks Lead to Low Noises and High Efficiency in Digital Integrated Circuits

Double power supplies are widely used in analog integrated circuits for the sake of power export and dynamic ranges. By contrast, single power supply and the ground line are regular in digital integrated circuits so far. In this paper, it is shown that double power supplies with cross-zero clocks help decrease the power consumption and noises in digital integrated circuits. They are firstly explained in frequency domain and then by a three-level energy system.

Reduction of total harmonic distortion of three-phase inverter using alternate switching strategy

Alternating current (AC) electrical drives mainly require smaller current (or torque) ripples and lower total harmonic distortion (THD) of voltage for excellent drive performances. Normally, in practice, to achieve these requirements, the inverter needs to be operated at high switching frequency. By operating at high switching frequency, the size of filter can be reduced. However, the inverter which oftenly employs insulated gate bipolar transistor (IGBT) for high power applications cannot be operated at high switching frequency. This is because, the IGBT switching frequency cannot be operated above 50 kHz due to its thermal restrictions. This paper proposes an alternate switching strategy to enable the use of IGBT for operating the inverter at high switching frequency to improve THD performances. In this strategy, each IGBT in a group of switches in the modified inverter circuit will operate the switching frequency at one-fourth of the inverter switching frequency. The alternate switching is implemented using simple analog and digital integrated circuits.

3.3V Transmitter Using 1.8V Transistors In A Cascode Configuration

A voltage-mode transmitter using a 1.8V-to-3.3V levelshifter and cascoded output buffer is proposed. 1.8V TSMC 65nm transistors are used. The design is targeted to meet JEDEC Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits DC Specifications as well as an AC transmission rate of 200 MHz on a 30 cm 50Ω board trace terminated with a 4 pF capacitive load. Overstress voltages will not be exceeded in order to avoid device failure due to breaching Gate Oxide Integrity, Hot Carrier Injection, or Negative Bias Temperature Instability.

Deep Graph Learning for Circuit Deobfuscation

Circuit obfuscation is a recently proposed defense mechanism to protect the intellectual property (IP) of digital integrated circuits (ICs) from reverse engineering. There have been effective schemes, such as satisfiability (SAT)-checking based attacks that can potentially decrypt obfuscated circuits, which is called deobfuscation. Deobfuscation runtime could be days or years, depending on the layouts of the obfuscated ICs. Hence, accurately pre-estimating the deobfuscation runtime within a reasonable amount of time is crucial for IC designers to optimize their defense. However, it is challenging due to (1) the complexity of graph-structured circuit; (2) the varying-size topology of obfuscated circuits; (3) requirement on efficiency for deobfuscation method. This study proposes a framework that predicts the deobfuscation runtime based on graph deep learning techniques to address the challenges mentioned above. A conjunctive normal form (CNF) bipartite graph is utilized to characterize the complexity of this SAT problem by analyzing the SAT attack method. Multi-order information of the graph matrix is designed to identify the essential features and reduce the computational cost. To overcome the difficulty in capturing the dynamic size of the CNF graph, an energy-based kernel is proposed to aggregate dynamic features into an identical vector space. Then, we designed a framework, Deep Survival Analysis with Graph (DSAG), which integrates energy-based layers and predicts runtime inspired by censored regression in survival analysis. Integrating uncensored data with censored data, the proposed model improves the standard regression significantly. DSAG is an end-to-end framework that can automatically extract the determinant features for deobfuscation runtime. Extensive experiments on benchmarks demonstrate its effectiveness and efficiency.

3.3V Transmitter Using 1.8V Transistors In A Cascode Configuration

A voltage-mode transmitter using a 1.8V-to-3.3V levelshifter and cascoded output buffer is proposed. 1.8V TSMC 65nm transistors are used. The design is targeted to meet JEDEC Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits DC Specifications as well as an AC transmission rate of 200 MHz on a 30 cm 50Ω board trace terminated with a 4 pF capacitive load. Overstress voltages will not be exceeded in order to avoid device failure due to breaching Gate Oxide Integrity, Hot Carrier Injection, or Negative Bias Temperature Instability.