35th International Symposium on Multiple-Valued Logic (ISMVL'05)
Latest Publications

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(FIVE YEARS 0)

Published By IEEE

0769523366

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Hahoe KAIST Robot Theatre: Learning Rules of Interactive Robot Behavior as a Multiple-Valued Logic Synthesis Problem

35th International Symposium on Multiple-Valued Logic (ISMVL'05) ◽

10.1109/ismvl.2005.18 ◽

2005 ◽

Cited By ~ 7

Author(s):

M. Perkowski ◽

T. Sasao ◽

Jong-Hwan Kim ◽

M. Lukac ◽

J. Allen ◽

...

Keyword(s):

Logic Synthesis ◽

Synthesis Problem ◽

Multiple Valued Logic ◽

Learning Rules ◽

Robot Behavior

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A Novel Ternary Switching Element Using CMOS Recharge Semi Floating-Gate Devices

35th International Symposium on Multiple-Valued Logic (ISMVL'05) ◽

10.1109/ismvl.2005.5 ◽

2005 ◽

Cited By ~ 2

Author(s):

H. Gundersen ◽

R. Jensen ◽

Y. Berg

Keyword(s):

Floating Gate ◽

Switching Element

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Polynomial Ring Calculus for Many-Valued Logics

35th International Symposium on Multiple-Valued Logic (ISMVL'05) ◽

10.1109/ismvl.2005.38 ◽

2005 ◽

Cited By ~ 4

Author(s):

W. Carnielli

Keyword(s):

Polynomial Ring

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Signed-digit CMOS (SD-CMOS) Logic Circuits with Dynamic Operation

35th International Symposium on Multiple-Valued Logic (ISMVL'05) ◽

10.1109/ismvl.2005.44 ◽

2005 ◽

Cited By ~ 1

Author(s):

H. Fukuda

Keyword(s):

Logic Circuits ◽

Dynamic Operation

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The Karhunen-Loève Transform of Discrete MVL Functions

35th International Symposium on Multiple-Valued Logic (ISMVL'05) ◽

10.1109/ismvl.2005.48 ◽

2005 ◽

Cited By ~ 1

Author(s):

M.A. Thornton

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Many-Valued Intuitionistic Implication and Inference Closure in a Bilattice-Based Logic

35th International Symposium on Multiple-Valued Logic (ISMVL'05) ◽

10.1109/ismvl.2005.22 ◽

2005 ◽

Cited By ~ 3

Author(s):

Z. Majkic

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Complete Bi-Decomposition of Multiple-Valued Functions Using MIN and MAX Gates

35th International Symposium on Multiple-Valued Logic (ISMVL'05) ◽

10.1109/ismvl.2005.14 ◽

2005 ◽

Cited By ~ 2

Author(s):

B. Steinbach ◽

C. Lang

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Three Dimensional Multi-Valued Design in Nanoscale Integrated Circuits

35th International Symposium on Multiple-Valued Logic (ISMVL'05) ◽

10.1109/ismvl.2005.49 ◽

2005 ◽

Author(s):

S.E. Lyshevski

Keyword(s):

Integrated Circuits ◽

Three Dimensional

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Partial Clones Determined by Concatenated Relations

35th International Symposium on Multiple-Valued Logic (ISMVL'05) ◽

10.1109/ismvl.2005.36 ◽

2005 ◽

Cited By ~ 1

Author(s):

L. Haddad ◽

I.G. Rosenberg

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A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors

35th International Symposium on Multiple-Valued Logic (ISMVL'05) ◽

10.1109/ismvl.2005.6 ◽

2005 ◽

Cited By ~ 6

Author(s):

K. Degawa ◽

T. Aoki ◽

H. Inokawa ◽

T. Higuchi ◽

Y. Takahashi

Keyword(s):

Single Electron ◽

Single Electron Transistors ◽

Cell Content ◽

Content Addressable Memory ◽

Electron Transistors

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35th International Symposium on Multiple-Valued Logic (ISMVL'05)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Hahoe KAIST Robot Theatre: Learning Rules of Interactive Robot Behavior as a Multiple-Valued Logic Synthesis Problem

A Novel Ternary Switching Element Using CMOS Recharge Semi Floating-Gate Devices

Polynomial Ring Calculus for Many-Valued Logics

Signed-digit CMOS (SD-CMOS) Logic Circuits with Dynamic Operation

The Karhunen-Loève Transform of Discrete MVL Functions

Many-Valued Intuitionistic Implication and Inference Closure in a Bilattice-Based Logic

Complete Bi-Decomposition of Multiple-Valued Functions Using MIN and MAX Gates

Three Dimensional Multi-Valued Design in Nanoscale Integrated Circuits

Partial Clones Determined by Concatenated Relations

A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors

35th International Symposium on Multiple-Valued Logic (ISMVL'05)
Latest Publications