2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
Latest Publications

TOTAL DOCUMENTS

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H-INDEX

(FIVE YEARS 0)

Published By IEEE

9781728128184

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation

2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2019.8771327 ◽

2019 ◽

Cited By ~ 1

Author(s):

Longfei Wang ◽

Ragh Kuttappa ◽

Baris Taskin ◽

Selcuk Kose

Keyword(s):

Voltage Noise ◽

Noise Mitigation ◽

Low Dropout Regulators ◽

On Chip

Security Network On-Chip for Mitigating Side-Channel Attacks

2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2019.8771328 ◽

2019 ◽

Author(s):

Farid Kenarangi ◽

Inna Partin-Vaisband

Keyword(s):

Network On Chip ◽

Side Channel ◽

Side Channel Attacks ◽

On Chip ◽

Security Network

Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems

2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2019.8771333 ◽

2019 ◽

Cited By ~ 1

Author(s):

Dylan Stow ◽

Itir Akgun ◽

Yuan Xie

Keyword(s):

Network On Chip ◽

Optimal Network ◽

On Chip

An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems

2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2019.8771330 ◽

2019 ◽

Author(s):

Chak-Wa Pui ◽

Gang Wu ◽

Freddy Y. C. Mang ◽

Evangeline F. Y. Young

Keyword(s):

Analytical Approach ◽

Time Division Multiplexing ◽

Time Division

FSNoC: Safe Network-on-Chip Design with Packet Level Lock Stepping

2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2019.8771331 ◽

2019 ◽

Author(s):

Zheng Xu ◽

Jacob Abraham

Keyword(s):

Network On Chip ◽

Chip Design ◽

On Chip

Bus-Invert Coding as a Low-Power Countermeasure Against Correlation Power Analysis Attack

2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2019.8771332 ◽

2019 ◽

Cited By ~ 1

Author(s):

M. Ali Vosoughi ◽

Longfei Wang ◽

Selcuk Kose

Keyword(s):

Low Power ◽

Power Analysis ◽

Correlation Power Analysis ◽

Power Analysis Attack

Communication Considerations for Silicon Interconnect Fabric

2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2019.8771326 ◽

2019 ◽

Cited By ~ 1

Author(s):

Boris Vaisband ◽

Subramanian S. Iyer

A Novel PUF Architecture Against Non-Invasive Attacks

2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) ◽

10.1109/slip.2019.8771329 ◽

2019 ◽

Author(s):

Yiming Wen ◽

Sayyed Farid Ahamed ◽

Weize Yu

Keyword(s):

Non Invasive

2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation

Security Network On-Chip for Mitigating Side-Channel Attacks

Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems

An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems

FSNoC: Safe Network-on-Chip Design with Packet Level Lock Stepping

Bus-Invert Coding as a Low-Power Countermeasure Against Correlation Power Analysis Attack

Communication Considerations for Silicon Interconnect Fabric

A Novel PUF Architecture Against Non-Invasive Attacks

2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
Latest Publications