Hot-carrier-induced circuit degradation for 0.18 μm CMOS technology

Author(s):  
Wei Li ◽  
Qiang Li ◽  
J.S. Yuan ◽  
J. McConkey ◽  
Yuan Chen ◽  
...  
Keyword(s):  
1988 ◽  
Vol 35 (12) ◽  
pp. 2210-2220 ◽  
Author(s):  
Chen Min-Liang ◽  
Leung Chung-Wai ◽  
W.T. Cochran ◽  
W. Jungling ◽  
C. Dziuba ◽  
...  

1994 ◽  
Vol 338 ◽  
Author(s):  
Xiao-Yu Li ◽  
Jen-Tai Hsu ◽  
Paul Aum ◽  
Vivek Bissessur ◽  
David Chan ◽  
...  

ABSTRACTPlasma etching can cause damage in gate oxide during ULSI processing. The damage in the oxide is believed to arise through a high field induced stress current. However, there is another type of damage which is due to ion and photon bombardment on the edge of poly-Si gate during the plasma etching. These two damage mechanisms impose different reliability problems. One is hot-carrier(HC) stress and the other is Fowler-Nordheim(F-N) stress. MOS devices with special test structures to assess plasma process damage were fabricated using 0.35 μm CMOS technology. The devices with different poly gate antennas and etching through different poly-Si gate etching conditions were studied using SEM and various electrical techniques. It was found that oxide charging damaged device is more susceptible to F-N type of stress while ion and photon bombardment damaged device is more susceptible to HC type of stress.


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