2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
Latest Publications

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Published By IEEE

9781509060375

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Ultra high density 3D SRAM cell design in Stacked Horizontal Nanowire (SN3D) fabric

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2017.8053734 ◽

2017 ◽

Cited By ~ 4

Author(s):

Naveen Macha ◽

Sandeep Geedipally ◽

Mostafizur Rahman

Keyword(s):

High Density ◽

Cell Design ◽

Sram Cell

A compact 8-bit adder design using in-memory memristive computing: Towards solving the Feynman Grand Prize challenge

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2017.8053712 ◽

2017 ◽

Cited By ~ 1

Author(s):

Dwaipayan Chakraborty ◽

Sunny Raj ◽

Sumit Kumar Jha

Keyword(s):

Grand Prize

Polymorphic spintronic logic gates for hardware security primitives — Device design and performance benchmarking

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2017.8053726 ◽

2017 ◽

Cited By ~ 1

Author(s):

S. Rakheja ◽

N. Kani

Keyword(s):

Hardware Security ◽

Logic Gates ◽

Device Design ◽

Performance Benchmarking ◽

Spintronic Logic ◽

And Performance

Proposal for novel magnetic memory device with spin momentum locking materials

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2017.8053717 ◽

2017 ◽

Cited By ~ 1

Author(s):

Xiaowan Qin ◽

Lang Zeng ◽

Tianqi Gao ◽

Deming Zhang ◽

Mingzhi Long ◽

...

Keyword(s):

Memory Device ◽

Magnetic Memory ◽

Spin Momentum

Transient model with interchangeability for dual-gate ambipolar CNTFET logic design

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2017.8053711 ◽

2017 ◽

Cited By ~ 1

Author(s):

Xuan Hu ◽

Joseph S. Friedman

Keyword(s):

Logic Design ◽

Transient Model ◽

Dual Gate

Approximate vector matrix multiplication implementations for neuromorphic applications using memristive crossbars

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2017.8053729 ◽

2017 ◽

Cited By ~ 3

Author(s):

Walt Woods ◽

Christof Teuscher

Keyword(s):

Matrix Multiplication ◽

Vector Matrix

Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2017.8053736 ◽

2017 ◽

Author(s):

Jiajun Shi ◽

Mingyu Li ◽

Csaba Andras Moritz

Keyword(s):

Power Delivery ◽

3D Ics ◽

Power Delivery Network ◽

Delivery Network

Hybrid neural network using binary RRAM devices

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2017.8053731 ◽

2017 ◽

Cited By ~ 1

Author(s):

Mohammed A. Zidan ◽

YeonJoo Jeong ◽

Wei D. Lu

Keyword(s):

Neural Network ◽

Hybrid Neural Network

Epsilon-greedy strategy for online dictionary learning with realistic memristor array constraints

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2017.8053730 ◽

2017 ◽

Cited By ~ 1

Author(s):

Fuxi Cai ◽

Wei D. Lu

Keyword(s):

Dictionary Learning ◽

Greedy Strategy ◽

Online Dictionary Learning ◽

Memristor Array

Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metal

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) ◽

10.1109/nanoarch.2017.8053737 ◽

2017 ◽

Author(s):

Karthik Yogendra ◽

Minsuk Koo ◽

Kaushik Roy

Keyword(s):

Heavy Metal ◽

Energy Efficient ◽

Bias Field ◽

Efficient Computation

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Ultra high density 3D SRAM cell design in Stacked Horizontal Nanowire (SN3D) fabric

A compact 8-bit adder design using in-memory memristive computing: Towards solving the Feynman Grand Prize challenge

Polymorphic spintronic logic gates for hardware security primitives — Device design and performance benchmarking

Proposal for novel magnetic memory device with spin momentum locking materials

Transient model with interchangeability for dual-gate ambipolar CNTFET logic design

Approximate vector matrix multiplication implementations for neuromorphic applications using memristive crossbars

Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS

Hybrid neural network using binary RRAM devices

Epsilon-greedy strategy for online dictionary learning with realistic memristor array constraints

Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metal

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
Latest Publications