Multi-scroll fractional-order chaotic system and finite-time synchronization

The definition of fractional calculus is introduced into the 5D chaotic system, and the 5D fractional-order chaotic system is obtained. The new 5D fractional-order chaotic system has no equilibrium, multi-scroll hidden attractor and multi-stability. By analyzing the time-domain waveform, phase diagram, bifurcation diagram and complexity, it is found that the system has no equilibrium but is very sensitive to parameters and initial values. With the variation of different parameters, the system can produce attractors of different scroll types accompanied by bursting oscillation. Secondly, the multi-stability of the hidden attractor is studied. Different initial values lead to the coexistence of attractors of different scroll number, which shows the advantages of the system. The correctness and realizability of the fractional-order chaotic system are proved by analog circuit and physical implement. Finally, because of the high security of multi-scroll attractor and hidden attractor, finite-time synchronization based on the fractional-order chaotic system is studied, which has a good application prospect in the field of secure communication.

Evolutionary Synthesis of Failure-Resilient Analog Circuits

Analog circuit design requires large amounts of human knowledge. A special case of circuit design is the synthesis of robust and failure-resilient electronics. Evolutionary algorithms can aid designers in exploring topologies with new properties. Here, we show how to encode a circuit topology with an upper-triangular incident matrix and use the NSGA-II algorithm to find computational circuits that are robust to component failure. Techniques for robustness evaluation and evolutionary algorithm guidances are described. As a result, we evolve square root and natural logarithm computational circuits that are robust to high-impedance or short-circuit malfunction of an arbitrary rectifying diode. We confirm the simulation results by hardware circuit implementation and measurements. We think that our research will inspire further searches for failure-resilient topologies.

Analog Circuit Fault Diagnosis Using a Novel Variant of aConvolutional Neural Network

Analog circuits play an important role in modern electronic systems. Aiming to accurately diagnose the faults of analog circuits, this paper proposes a novel variant of a convolutional neural network, namely, a multi-scale convolutional neural network with a selective kernel (MSCNN-SK). In MSCNN-SK, a multi-scale average difference layer is developed to compute multi-scale average difference sequences, and then these sequences are taken as the input of the model, which enables it to mine potential fault characteristics. In addition, a dynamic convolution kernel selection mechanism is introduced to adaptively adjust the receptive field, so that the feature extraction ability of MSCNN-SK is enhanced. Based on two well-known fault diagnosis circuits, comparison experiments are conducted, and experimental results show that our proposed method achieves higher performance.

Performance Analysis of PWM Based Full Wave Bridge Inverter

An obvious device for the utilization of renewable energy sources is inverter and Pulse Width Modulation technique is widely used method for voltage source inverters. This paper deals with the generation of PWM signals by analog circuit, where the comparison of sine wave and sawtooth wave for the operation of power circuit takes place. The above mentioned technique is studied and verified by Simulating the circuit. The prototype of PWM based, single phase, full bridge inverter is developed and the results are verified for the nominal voltage and frequency with the help of simulation and hardware is designed. Keywords: Inverter, SPWM, VSI, Simulation, MATLAB

Mapping the BCPNN Learning Rule to a Memristor Model

The Bayesian Confidence Propagation Neural Network (BCPNN) has been implemented in a way that allows mapping to neural and synaptic processes in the human cortexandhas been used extensively in detailed spiking models of cortical associative memory function and recently also for machine learning applications. In conventional digital implementations of BCPNN, the von Neumann bottleneck is a major challenge with synaptic storage and access to it as the dominant cost. The memristor is a non-volatile device ideal for artificial synapses that fuses computation and storage and thus fundamentally overcomes the von Neumann bottleneck. While the implementation of other neural networks like Spiking Neural Network (SNN) and even Convolutional Neural Network (CNN) on memristor has been studied, the implementation of BCPNN has not. In this paper, the BCPNN learning rule is mapped to a memristor model and implemented with a memristor-based architecture. The implementation of the BCPNN learning rule is a mixed-signal design with the main computation and storage happening in the analog domain. In particular, the nonlinear dopant drift phenomenon of the memristor is exploited to simulate the exponential decay of the synaptic state variables in the BCPNN learning rule. The consistency between the memristor-based solution and the BCPNN learning rule is simulated and verified in Matlab, with a correlation coefficient as high as 0.99. The analog circuit is designed and implemented in the SPICE simulation environment, demonstrating a good emulation effect for the BCPNN learning rule with a correlation coefficient as high as 0.98. This work focuses on demonstrating the feasibility of mapping the BCPNN learning rule to in-circuit computation in memristor. The feasibility of the memristor-based implementation is evaluated and validated in the paper, to pave the way for a more efficient BCPNN implementation, toward a real-time brain emulation engine.