Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Static and Dynamic Power Reduction by Architecture Selection

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11847083_65 ◽

2006 ◽

pp. 659-668 ◽

Cited By ~ 6

Author(s):

Christian Piguet ◽

Christian Schuster ◽

Jean-Luc Nagel

Keyword(s):

Power Reduction ◽

Dynamic Power

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The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11847083_41 ◽

2006 ◽

pp. 425-438 ◽

Cited By ~ 1

Author(s):

Yijun Liu ◽

Steve Furber ◽

Zhenkun Li

Keyword(s):

Low Power ◽

Hierarchical Processing

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System Level Multi-bank Main Memory Configuration for Energy Reduction

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11847083_9 ◽

2006 ◽

pp. 84-94 ◽

Cited By ~ 3

Author(s):

Hanene Ben Fradj ◽

Cécile Belleudy ◽

Michel Auguin

Keyword(s):

Main Memory ◽

Energy Reduction ◽

System Level

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The Holy Grail of Holistic Low-Power Design

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11847083_68 ◽

2006 ◽

pp. 671-671

Author(s):

F. Pessolano

Keyword(s):

Low Power ◽

Low Power Design ◽

Holy Grail

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Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11847083_61 ◽

2006 ◽

pp. 624-633 ◽

Cited By ~ 1

Author(s):

M. Alioto ◽

M. Poli ◽

S. Rocchi ◽

V. Vignoli

Keyword(s):

Power Analysis ◽

Differential Power Analysis

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Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11847083_48 ◽

2006 ◽

pp. 496-503

Author(s):

Jürgen Rauscher ◽

Hans-Jörg Pfleiderer

Keyword(s):

Power Supply ◽

Current Waveform

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Delay Constrained Register Transfer Level Dynamic Power Estimation

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11847083_4 ◽

2006 ◽

pp. 36-46 ◽

Cited By ~ 1

Author(s):

Sriram Sambamurthy ◽

Jacob A. Abraham ◽

Raghuram S. Tupuri

Keyword(s):

Power Estimation ◽

Register Transfer Level ◽

Dynamic Power ◽

Register Transfer

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Modeling of Crosstalk Fault in Defective Interconnects

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11847083_33 ◽

2006 ◽

pp. 340-349

Author(s):

Ajoy K. Palit ◽

Kishore K. Duganapalli ◽

Walter Anheier

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Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11847083_21 ◽

2006 ◽

pp. 214-224 ◽

Cited By ~ 2

Author(s):

A. Chakraborty ◽

K. Duraisami ◽

A. Sathanur ◽

P. Sithambaram ◽

A. Macii ◽

...

Keyword(s):

Clock Skew ◽

Dynamic Management ◽

Thermally Induced

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Two Efficient Synchronous $\Leftrightarrow$ Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11847083_19 ◽

2006 ◽

pp. 191-202 ◽

Cited By ~ 5

Author(s):

A. Sheibanyrad ◽

A. Greiner

Keyword(s):

Network On Chip ◽

On Chip

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Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer Berlin Heidelberg

Static and Dynamic Power Reduction by Architecture Selection

The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing

System Level Multi-bank Main Memory Configuration for Energy Reduction

The Holy Grail of Holistic Low-Power Design

Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis

Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations

Delay Constrained Register Transfer Level Dynamic Power Estimation

Modeling of Crosstalk Fault in Defective Interconnects

Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective

Two Efficient Synchronous $\Leftrightarrow$ Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures

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Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and SimulationLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By Springer Berlin Heidelberg

Static and Dynamic Power Reduction by Architecture Selection

The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing

System Level Multi-bank Main Memory Configuration for Energy Reduction

The Holy Grail of Holistic Low-Power Design

Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis

Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations

Delay Constrained Register Transfer Level Dynamic Power Estimation

Modeling of Crosstalk Fault in Defective Interconnects

Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective

Two Efficient Synchronous $\Leftrightarrow$ Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Latest Publications