A constructive heuristic for application mapping onto an express channel based Network-on-Chip

2015 ◽  
Author(s):  
Sandeep D'souza ◽  
J. Soumya ◽  
Santanu Chattopadhyay
Keyword(s):  
Network On Chip ◽  
Application Mapping ◽  
Constructive Heuristic ◽  
On Chip

Application mapping onto mesh-based network-on-chip using constructive heuristic algorithms

2016 ◽  
Vol 72 (11) ◽  
pp. 4365-4378 ◽  
Author(s):  
Chi-Hsiang Cheng ◽  
Wei-Mei Chen
Keyword(s):  
Heuristic Algorithms ◽  
Network On Chip ◽  
Application Mapping ◽  
Constructive Heuristic ◽  
On Chip

A Constructive Heuristic for Application Mapping onto Mesh Based Network-on-Chip

2015 ◽  
Vol 24 (08) ◽  
pp. 1550126 ◽  
Author(s):  
Pradip Kumar Sahu ◽  
Kanchan Manna ◽  
Tapan Shah ◽  
Santanu Chattopadhyay
Keyword(s):  
Complexity Analysis ◽  
Network On Chip ◽  
Application Mapping ◽  
Design Time ◽  
Constructive Heuristic ◽  
Underlying Network ◽  
Dynamic Performances ◽  
Self Similar ◽  
On Chip ◽  
Better Than

Mapping constitutes a very important step in network-on-chip (NoC)-based implementation of an application. An application is often represented in the form of an application core graph. The cores of the core graph communicate between themselves using the underlying network. This paper presents a constructive heuristic to statically map applications on two-dimensional mesh-connected NoC. The approach corresponds to a design time decision of attachment of cores to the routers. The mapping results, in terms of overall communication cost metric, have been compared with many well-known techniques reported in the literature and also with an exact method built around integer linear programming (ILP). A thorough complexity analysis of the algorithm has been performed. For smaller benchmarks, the results obtained are same as those for the ILP generated solutions. For benchmarks containing 64 and higher number of cores, the mapping solutions are better than the existing ones. Dynamic performances of the mapped solutions have been compared with respect to synthetically generated self-similar traffic. In many cases, our approach requires less latency and energy per packet than the existing methods while providing higher throughput.

Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip

2021 ◽  
Vol 116 ◽  
pp. 102026
Author(s):  
P. Veda Bhanu ◽  
Soumya J.
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Application Mapping ◽  
On Chip

Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach

Integration ◽  
2021 ◽  
Author(s):  
Nizar Dahir ◽  
Ammar Karkar ◽  
Maurizio Palesi ◽  
Terrence Mak ◽  
Alex Yakovlev
Keyword(s):  
Power Density ◽  
Network On Chip ◽  
Multi Objective ◽  
Application Mapping ◽  
On Chip

Application Mapping on Network-on-Chip

2018 ◽  
pp. 119-154
Author(s):  
Santanu Kundu ◽  
Santanu Chattopadhyay
Keyword(s):  
Network On Chip ◽  
Application Mapping ◽  
On Chip

LPNet: A DNN based latency prediction technique for application mapping in Network-on-Chip design

2021 ◽  
pp. 104370
Author(s):  
Sambangi Ramesh ◽  
Manghnani Hitesh ◽  
Santanu Chattopadhyay
Keyword(s):  
Network On Chip ◽  
Chip Design ◽  
Application Mapping ◽  
Prediction Technique ◽  
On Chip

Extending Kernighan–Lin partitioning heuristic for application mapping onto Network-on-Chip

2014 ◽  
Vol 60 (7) ◽  
pp. 562-578 ◽  
Author(s):  
Pradip Kumar Sahu ◽  
Kanchan Manna ◽  
Nisarg Shah ◽  
Santanu Chattopadhyay
Keyword(s):  
Network On Chip ◽  
Application Mapping ◽  
On Chip

Dynamic Application Mapping Algorithm for Wireless Network-on-Chip

2015 ◽  
Author(s):  
Amin Rezaei ◽  
Masoud Daneshtalab ◽  
Danella Zhao ◽  
Farshad Safaei ◽  
Xiaohang Wang ◽  
...  
Keyword(s):  
Wireless Network ◽  
Network On Chip ◽  
Mapping Algorithm ◽  
Application Mapping ◽  
On Chip
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