2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
Latest Publications

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Published By IEEE

9781479930975

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3D stacking of high-performance processors

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) ◽

10.1109/hpca.2014.6835959 ◽

2014 ◽

Cited By ~ 11

Author(s):

Philip Emma ◽

Alper Buyuktosunoglu ◽

Michael Healy ◽

Krishnan Kailas ◽

Valentin Puente ◽

...

Keyword(s):

High Performance ◽

3D Stacking

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Understanding the impact of gate-level physical reliability effects on whole program execution

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) ◽

10.1109/hpca.2014.6835976 ◽

2014 ◽

Cited By ~ 8

Author(s):

Raghuraman Balasubramanian ◽

Karthikeyan Sankaralingam

Keyword(s):

Program Execution ◽

The Impact

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Low-overhead and high coverage run-time race detection through selective meta-data management

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) ◽

10.1109/hpca.2014.6835979 ◽

2014 ◽

Cited By ~ 3

Author(s):

Ruirui Huang ◽

Erik Halberg ◽

Andrew Ferraiuolo ◽

G. Edward Suh

Keyword(s):

Data Management ◽

High Coverage ◽

Meta Data ◽

Race Detection ◽

Run Time

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QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) ◽

10.1109/hpca.2014.6835942 ◽

2014 ◽

Cited By ~ 18

Author(s):

Dominic DiTomaso ◽

Avinash Kodi ◽

Ahmed Louri

Keyword(s):

Fault Tolerant ◽

Network On Chip ◽

Power Efficient ◽

On Chip

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Atomic SC for simple in-order processors

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) ◽

10.1109/hpca.2014.6835950 ◽

2014 ◽

Cited By ~ 11

Author(s):

Dibakar Gope ◽

Mikko H. Lipasti

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Spare register aware prefetching for graph algorithms on GPUs

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) ◽

10.1109/hpca.2014.6835970 ◽

2014 ◽

Cited By ~ 22

Author(s):

Nagesh B. Lakshminarayana ◽

Hyesoon Kim

Keyword(s):

Graph Algorithms

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MemZip: Exploring unconventional benefits from memory compression

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) ◽

10.1109/hpca.2014.6835972 ◽

2014 ◽

Cited By ~ 46

Author(s):

Ali Shafiee ◽

Meysam Taassori ◽

Rajeev Balasubramonian ◽

Al Davis

Keyword(s):

Memory Compression

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Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) ◽

10.1109/hpca.2014.6835953 ◽

2014 ◽

Cited By ~ 16

Author(s):

Amin Ansari ◽

Asit Mishra ◽

Jianping Xu ◽

Josep Torrellas

Keyword(s):

Energy Efficient ◽

Dynamic Voltage ◽

On Chip

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NUAT: A non-uniform access time memory controller

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) ◽

10.1109/hpca.2014.6835956 ◽

2014 ◽

Cited By ~ 26

Author(s):

Wongyu Shin ◽

Jeongmin Yang ◽

Jungwhan Choi ◽

Lee-Sup Kim

Keyword(s):

Access Time ◽

Memory Controller

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TSO-CC: Consistency directed cache coherence for TSO

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA) ◽

10.1109/hpca.2014.6835927 ◽

2014 ◽

Cited By ~ 30

Author(s):

Marco Elver ◽

Vijay Nagarajan

Keyword(s):

Cache Coherence

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2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

3D stacking of high-performance processors

Understanding the impact of gate-level physical reliability effects on whole program execution

Low-overhead and high coverage run-time race detection through selective meta-data management

QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers

Atomic SC for simple in-order processors

Spare register aware prefetching for graph algorithms on GPUs

MemZip: Exploring unconventional benefits from memory compression

Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks

NUAT: A non-uniform access time memory controller

TSO-CC: Consistency directed cache coherence for TSO

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
Latest Publications