2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

Reliability-Aware Multi-Vth Domain Digital Design Assessment

2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) ◽

10.1109/ddecs.2018.00007 ◽

2018 ◽

Author(s):

Theodor Hillebrand ◽

Ludwig Karsthof ◽

Steffen Paul ◽

Dagmar Peters-Drolshagen

Keyword(s):

Digital Design ◽

Design Assessment

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Natural Language Based Power Domain Partitioning

2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) ◽

10.1109/ddecs.2018.00025 ◽

2018 ◽

Author(s):

David Lemma ◽

Daniel GroBe ◽

Rolf Drechsler

Keyword(s):

Natural Language ◽

Power Domain ◽

Domain Partitioning

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A Novel TFET 8T-SRAM Cell with Improved Noise Margin and Stability

2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) ◽

10.1109/ddecs.2018.00014 ◽

2018 ◽

Cited By ~ 3

Author(s):

Seyed Hamid Fani ◽

Ali Peiravi ◽

Hooman Farkhani ◽

Farshad Moradi

Keyword(s):

Noise Margin ◽

Sram Cell

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Software-Level TMR Approach for On-Board Data Processing in Space Applications

2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) ◽

10.1109/ddecs.2018.00033 ◽

2018 ◽

Cited By ~ 1

Author(s):

Karl Janson ◽

Carl Johann Treudler ◽

Thomas Hollstein ◽

Jaan Raik ◽

Maksim Jenihhin ◽

...

Keyword(s):

Data Processing ◽

Space Applications

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Augmenting All Solution SAT Solving for Circuits with Structural Information

2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) ◽

10.1109/ddecs.2018.00028 ◽

2018 ◽

Author(s):

Abraham Temesgen Tibebu ◽

Goerschwin Fey

Keyword(s):

Structural Information ◽

Sat Solving

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Design and Performance Analysis of Ultra-Low Voltage Rail-to-Rail Comparator in 130 nm CMOS Technology

2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) ◽

10.1109/ddecs.2018.00016 ◽

2018 ◽

Cited By ~ 5

Author(s):

Lukas Nagy ◽

Daniel Arbet ◽

Martin Kovac ◽

Miroslav Potocny ◽

Viera Stopjakova

Keyword(s):

Performance Analysis ◽

Low Voltage ◽

Cmos Technology ◽

Rail To Rail ◽

And Performance

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Superpixel Accelerator for Computer Vision Applications on Arria 10 SoC

2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) ◽

10.1109/ddecs.2018.00-12 ◽

2018 ◽

Cited By ~ 6

Author(s):

Amila Akagic ◽

Emir Buza ◽

Razija Turcinhodzic ◽

Hana Haseljic ◽

Noda Hiroyuki ◽

...

Keyword(s):

Computer Vision ◽

Computer Vision Applications

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[Copyright notice]

2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) ◽

10.1109/ddecs.2018.00003 ◽

2018 ◽

Keyword(s):

Copyright Notice

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On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits

2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) ◽

10.1109/ddecs.2018.00022 ◽

2018 ◽

Cited By ~ 4

Author(s):

Marcello Traiola ◽

Arnaud Virazel ◽

Patrick Girard ◽

Mario Barbareschi ◽

Alberto Bosio

Keyword(s):

Integrated Circuits

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Tuning Stochastic Space Compaction to Faster-than-at-Speed Test

2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) ◽

10.1109/ddecs.2018.00020 ◽

2018 ◽

Cited By ~ 1

Author(s):

Alexander Sprenger ◽

Sybille Hellebrand

Keyword(s):

Speed Test ◽

Stochastic Space

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2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Reliability-Aware Multi-Vth Domain Digital Design Assessment

Natural Language Based Power Domain Partitioning

A Novel TFET 8T-SRAM Cell with Improved Noise Margin and Stability

Software-Level TMR Approach for On-Board Data Processing in Space Applications

Augmenting All Solution SAT Solving for Circuits with Structural Information

Design and Performance Analysis of Ultra-Low Voltage Rail-to-Rail Comparator in 130 nm CMOS Technology

Superpixel Accelerator for Computer Vision Applications on Arria 10 SoC

[Copyright notice]

On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits

Tuning Stochastic Space Compaction to Faster-than-at-Speed Test

Export Citation Format

2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Reliability-Aware Multi-Vth Domain Digital Design Assessment

Natural Language Based Power Domain Partitioning

A Novel TFET 8T-SRAM Cell with Improved Noise Margin and Stability

Software-Level TMR Approach for On-Board Data Processing in Space Applications

Augmenting All Solution SAT Solving for Circuits with Structural Information

Design and Performance Analysis of Ultra-Low Voltage Rail-to-Rail Comparator in 130 nm CMOS Technology

Superpixel Accelerator for Computer Vision Applications on Arria 10 SoC

[Copyright notice]

On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits

Tuning Stochastic Space Compaction to Faster-than-at-Speed Test

2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
Latest Publications