Embedded Memories for Cryogenic Applications

The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

Design and Analysis of Soft Error Rate in FET/CNTFET Based Radiation Hardened SRAM Cell

Aerospace equipages encounter potential radiation footprints through which soft errors occur in the memories onboard. Hence, robustness against radiation with reliability in memory cells is a crucial factor in aerospace electronic systems. This work proposes a novel Carbon nanotube field-effect transistor (CNTFET) in designing a robust memory cell to overcome these soft errors. Further, a petite driver circuit to test the SRAM cells which serve the purpose of precharge and sense amplifier, and has a reduction in threefold of transistor count is recommended. Additionally, analysis of robustness against radiation in varying memory cells is carried out using standard GPDK 90 nm, GPDK 45 nm, and 14 nm CNTFET. The reliability of memory cells depends on the critical charge of a device, and it is tested by striking an equivalent current charge of the cosmic ray’s linear energy transfer (LET) level. Also, the robustness of the memory cell is tested against the variation in process, voltage and temperature. Though CNTFET surges with high power consumption, it exhibits better noise margin and depleted access time. GPDK 45 nm has an average of 40% increase in SNM and 93% reduction of power compared to the 14 nm CNTFET with 96% of surge in write access time. Thus, the conventional MOSFET’s 45 nm node outperforms all the configurations in terms of static noise margin, power, and read delay which swaps with increased write access time.

Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness TILD (=10, 100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits.

A loadless 4T SRAM powered by gate leakage current with a high tolerance for fluctuations in device parameters

A novel loadless four-transistor static random access memory cell is proposed that consists of two N-type driver MOSFETs and two P-type access ones whose gate leakage currents from word-line are used for holding data in the cell. It is shown that the proposed cell has a higher tolerance for manufacturing device fluctuations compared with the conventional loadless 4T SRAM. Furthermore, it is free from bit-line disturb in contrast to the conventional cell. It is confirmed by simulation in 32nm technology node that the read static noise margin of the proposed cell reaches 138.7% of the six-transistor SRAM cell and that the hold static noise margin can be acceptable when the gate insulator thickness of the P-type access MOSFETs is made thinner than the N-type driver MOSFETs. The retention current for the proposed cell decreases to 66.7% of the 6TSRAM and the data rate in read increases to 125%.

Printed dual-gate organic thin film transistors and PMOS inverters on flexible substrates: Role of top gate electrode

We report printed single and dual-gate organic thin film transistors (OTFTs) and PMOS inverters fabricated on 125 µm-thick flexible polyethylene naphthalate (PEN) substrate. All the electrodes (gate, source, and drain) are inkjet-printed, while the parylene dielectric is formed by chemical vapor deposition. A dispenser system is used to print the active channel material using a blend of 2,7-dihexyl-dithieno[2,3-d;2',3'-d']benzo[1,2-b;4,5-b']dithiophene (DTBDT-C6) and polystyrene (PS) in tetralin solvent, which gives highest mobility of 0.43 cm2/Vs. Dual-gate OTFTs are characterized by keeping the other gate electrode either in grounded or floating state. Floating gate electrode devices shows higher apparent mobility and current ratio due to additional capacitance of the parylene dielectric. PMOS inverter circuits are characterized in terms of gain, trip point and noise margin values calculated from the voltage transfer characteristics (VTC). Applied top gate voltage on the load OTFT control the conductivity or threshold voltage (VTh) of the bottom TFT and shift the trip point towards the middle of the VTC curve, and hence increase the noise margin.

Performance Analysis of 6T SRAM and ONOFIC Cells

Background: As the Technology node scales down to deep sub-micron regime, the design of static random-access memory (SRAM) cell becomes a critical issue because of increased leakage current components. These leakage current components prevent to design a low power processor as large of the processor power is consumed by the memory part. Objective: In this paper, a SRAM cell is designed based on ON/OFF logic (ONOFIC) approach. Static noise margin (SNM) of the cell for the different states are calculated and evaluated by using butterfly as well as noise (N) curves with the help of Cadence tools at 45 nm technology node. Methods: ONOFIC approach helps to reduce the leakage current components which makes a low power memory cell. A performance comparison is made between the conventional six-transistor (6T) SRAM cell and memory cell using ONOFIC approach. Results: Low value of power delay product (PDP) is the outcome of ONOFIC approach as compared to conventional cell. ONOFIC approach decreases PDP by 99.99% in case of hold state. Conclusions: ONOFIC approach improves the different performance metrics for the different states of the SRAM cell.

Self-heating effect on logic performance of 6T-SRAM based on CFET device

CFET devices have become emerging and promising candidates for continuing Moore's law at sub-3 nm nodes owing to the area advantage of the N-P stacked structure, which markedly improves the integration of circuits. However, the introduction of vertical structure leads to severe thermal issues due to the self-heating effect, resulting in the degradation of the device and circuit performance. This paper mainly evaluates and analyzes the performance of the SRAM unit built using the CFET structure. The CFET-SRAM exhibits better performance than the conventional CMOS-SRAM in terms of access delay, even with the impact of self-heating. For the multi-fin-based CFET, although the total gate capacitance increases, the enhanced current improves the static noise margin significantly. However, as the number of channels expands, sheet-based CFET devices show more comprehensive superiority of area and performance.

Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor

Ternary logic has been demonstrated as a superior contrasting option to binary logic. This paper presents a ternary subtractor circuit in which the input signal is converted into binary. The proposed design is implemented using Carbon Nanotube Field Effect Transistor (CNTFET), a forefront innovation. A correlation has been made in the proposed design on parameters like Power-Delay Product (PDP), Energy Delay Product (EDP), average power consumption, delay and static noise margin. Every one of these parameters is obtained by simulating the circuits on the HSPICE simulator. The proposed design indicates an improvement of 60.14%, 59.34%, 74.98% and 84.28%, respectively, in power consumption, delay, PDP and EDP individually in correlation with recent designs. The increased carbon nanotubes least affect the proposed subtractor design. In noise analysis, the proposed design outperformed all the existing designs.

A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications

An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows × 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 μW and 3.82 μW, while the average energy consumption is only 0.39 pJ.

A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs

The double gate junctionless transistor (DG-JLT) has become the most promising device in sub nano-meter regime. DGJLT based circuits have improved performance and simpler fabrication than their inversion mode counterparts. This paper demonstrates the design of different analog and digital circuits using DGJLT. Amplifiers and inverters are the basic building block of electronic ICs. A MOS amplifier converts the variation of the gate to source voltage to a small current under transconductance and hence, the output voltage. A single-stage amplifier and differential amplifier have been designed with junctionless-double-gate (JL-DG) MOSFET. Trans-conductance, output voltage, and gain have been investigated using ATLAS 2D device simulator. The inverter is the primary logic gate that can be used to verify the device's response in digital applications. Further, CMOS inverter have been designed using JL-DG MOSFET, and its performance parameters such as switching voltage, noise margin, and logic delay have been analyzed. A switching voltage of 0.43 V, noise margin of 0.265 V, and a delay of 19.18 psec have been obtained for the basic cell. CMOS inverter using JL-DG MOSFET at 20 nm technology node have prompted better performance results. Thus, The JL-DG MOSFET has a bright future in low-power analog and digital applications.