scholarly journals Toward High-Performance Polymer Photovoltaic Devices for Low-Power Indoor Applications (Solar RRL 12∕2017)

Solar RRL ◽  
2017 ◽  
Vol 1 (12) ◽  
pp. 1770143
Author(s):  
Shun-Shing Yang ◽  
Zong-Chun Hsieh ◽  
Muchamed L. Keshtov ◽  
Ganesh D. Sharma ◽  
Fang-Chung Chen
Solar RRL ◽  
2017 ◽  
Vol 1 (12) ◽  
pp. 1700174 ◽  
Author(s):  
Shun-Shing Yang ◽  
Zong-Chun Hsieh ◽  
Muchamed L. Keshtov ◽  
Ganesh D. Sharma ◽  
Fang-Chung Chen

2018 ◽  
Vol 42 (11) ◽  
pp. 8960-8967 ◽  
Author(s):  
Yang Miao ◽  
Yincai Xu ◽  
Yuewei Zhang ◽  
Xianju Yan ◽  
Kaiqi Ye ◽  
...  

Water/alcohol-soluble 3D-structured spirobifluorene based cathode interlayers (CILs) were synthesized and employed to fabricate high performance polymer solar cells (PSCs).


2010 ◽  
Vol 20 (13) ◽  
pp. 2575 ◽  
Author(s):  
Li-Min Chen ◽  
Zheng Xu ◽  
Ziruo Hong ◽  
Yang Yang

2009 ◽  
Vol 93 (9) ◽  
pp. 1681-1684 ◽  
Author(s):  
Motoshi Nakamura ◽  
Chunhe Yang ◽  
Keisuke Tajima ◽  
Kazuhito Hashimoto

Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.


Author(s):  
Hiroyuki Hakoi ◽  
Ming Ni ◽  
Junichi Hashimoto ◽  
Takashi Sato ◽  
Shinji Shimada ◽  
...  

2018 ◽  
Vol 69 (4) ◽  
pp. 890-893
Author(s):  
Sorana Baciu ◽  
Cristian Berece ◽  
Adrian Florea ◽  
Andrada Voina Tonea ◽  
Ondine Lucaciu ◽  
...  

In this study were compared two investigation methods, a bi- and tri-dimensional techniques by examining the marginal fit pressed in (BioHPP) Inlays. The study pruved that the BioHPP is a high performance polymer which provides very good clinical results.


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