Galois LFSR, Embedded Devices and Side Channel Weaknesses

2006 ◽  
pp. 436-451 ◽  
Author(s):  
Antoine Joux ◽  
Pascal Delaunay
Keyword(s):  
Side Channel ◽  
Embedded Devices

On the Worst-Case Side-Channel Security of ECC Point Randomization in Embedded Devices

2020 ◽  
pp. 205-227
Author(s):  
Melissa Azouaoui ◽  
François Durvaux ◽  
Romain Poussier ◽  
François-Xavier Standaert ◽  
Kostas Papagiannopoulos ◽  
...  
Keyword(s):  
Side Channel ◽  
Embedded Devices ◽  
Worst Case

Effect of side channel attacks on RSA embedded devices

2007 ◽  
Author(s):  
Santosh Ghosh ◽  
Monjur Alam ◽  
Dipanwita Roy Chowdhury ◽  
Indranil Sen Gupta
Keyword(s):  
Side Channel ◽  
Side Channel Attacks ◽  
Embedded Devices

scholarly journals Detecting Faults in Inner-Product Masking Scheme - IPM-FD: IPM with Fault Detection

10.29007/fv2n ◽  
2019 ◽  
Author(s):  
Wei Cheng ◽  
Claude Carlet ◽  
Kouassi Goli ◽  
Jean-Luc Danger ◽  
Sylvain Guilley
Keyword(s):  
Fault Detection ◽  
Fault Injection ◽  
Inner Product ◽  
Side Channel ◽  
Embedded Devices ◽  
Side Channel Analysis ◽  
Injection Attacks ◽  
Word Level ◽  
Channel Analysis ◽  
Fault Injection Attacks

Side-channel analysis and fault injection attacks are two typical threats to cryptographic implementations, especially in modern embedded devices. Thus there is an insistent demand for dual side-channel and fault injection protections. As it is known, masking scheme is a kind of provable countermeasures against side-channel attacks. Recently, inner product masking (IPM) was proposed as a promising higher-order masking scheme against side-channel analysis, but not for fault injection attacks. In this paper, we devise a new masking scheme named IPM-FD. It is built on IPM, which enables fault detection. This novel masking scheme has three properties: the security orders in the word-level probing model, bit-level probing model, and the number of detected faults. IPM-FD is proven secure both in the word-level and in the bit-level probing models, and allows for end-to-end fault detection against fault injection attacks.Furthermore, we illustrate its security order by linking it to one defining parameters of linear code, and show its implementation cost by applying IPM-FD to AES-128.

Design Time Engineering of Side Channel Resistant Cipher Implementations

2013 ◽  
pp. 133-157 ◽  
Author(s):  
Alessandro Barenghi ◽  
Luca Breveglieri ◽  
Fabrizio De Santis ◽  
Filippo Melzani ◽  
Andrea Palomba ◽  
...  
Keyword(s):  
Power Consumption ◽  
Information Leakage ◽  
Smart Phones ◽  
Mobile Systems ◽  
Side Channel ◽  
Security Level ◽  
Embedded Devices ◽  
Design Time ◽  
Secret Keys ◽  
Channel Information

Dependable and trustworthy security solutions have emerged as a crucial requirement in the specification of the applications and protocols employed in modern Information Systems (IS). Threats to the security of embedded devices, such as smart phones and PDAs, have been growing since several techniques exploiting side-channel information leakage have proven successful in recovering secret keys even from complex mobile systems. This chapter summarizes the side-channel techniques based on power consumption and elaborates the issue of the design time engineering of a secure system, through the employment of the current hardware design tools. The results of the analysis show how these tools can be effectively used to understand possible vulnerabilities to power consumption side-channel attacks, thus providing a sound conservative margin on the security level. The possible extension of this methodology to the case of fault attacks is also sketched.

scholarly journals The Uncertainty of Side-channel Analysis: A Way to Leverage from Heuristics

2021 ◽  
Vol 17 (3) ◽  
pp. 1-27
Author(s):  
Unai Rioja ◽  
Servio Paguada ◽  
Lejla Batina ◽  
Igor Armendariz
Keyword(s):  
Six Sigma ◽  
Security Analysis ◽  
Side Channel ◽  
Security Analysts ◽  
Embedded Devices ◽  
Side Channel Analysis ◽  
Analysis Process ◽  
Channel Analysis ◽  
Optimal Values ◽  
Six Sigma Methodology

Performing a comprehensive side-channel analysis evaluation of small embedded devices is a process known for its variability and complexity. In real-world experimental setups, the results are largely influenced by a huge amount of parameters, some of which are not easily adjusted without trial and error and are heavily relying on the experience of professional security analysts. In this article, we advocate the usage of an existing statistical methodology called Six Sigma (6 ) for side-channel analysis optimization. This well-known methodology is commonly used in other industrial fields, such as production and quality engineering, to reduce the variability of industrial processes. We propose a customized Six Sigma methodology, which allows even a less-experienced security analysis to select optimal values for the different variables that are critical for the side-channel analysis procedure. Moreover, we show how our methodology helps in improving different phases in the side-channel analysis process.

PRIMER: Profiling Interrupts using Electromagnetic Side-Channel for Embedded Devices

2021 ◽  
pp. 1-1
Author(s):  
Moumita Dey ◽  
Baki Berkay Yilmaz ◽  
Milos Prvulovic ◽  
Alenka Zajic
Keyword(s):  
Side Channel ◽  
Embedded Devices

scholarly journals Revisiting a Methodology for Efficient CNN Architectures in Profiling Attacks

2020 ◽  
pp. 147-168
Author(s):  
Lennert Wouters ◽  
Victor Arribas ◽  
Benedikt Gierlichs ◽  
Bart Preneel
Keyword(s):  
Critical Review ◽  
Academic Research ◽  
Side Channel ◽  
Data Sets ◽  
Embedded Devices ◽  
Side Channel Analysis ◽  
Similar Performance ◽  
Public Data ◽  
Filter Size ◽  
Channel Analysis

This work provides a critical review of the paper by Zaid et al. titled “Methodology for Efficient CNN Architectures in Profiling attacks”, which was published in TCHES Volume 2020, Issue 1. This work studies the design of CNN networks to perform side-channel analysis of multiple implementations of the AES for embedded devices. Based on the authors’ code and public data sets, we were able to cross-check their results and perform a thorough analysis. We correct multiple misconceptions by carefully inspecting different elements of the model architectures proposed by Zaid et al. First, by providing a better understanding on the internal workings of these models, we can trivially reduce their number of parameters on average by 52%, while maintaining a similar performance. Second, we demonstrate that the convolutional filter’s size is not strictly related to the amount of misalignment in the traces. Third, we show that increasing the filter size and the number of convolutions actually improves the performance of a network. Our work demonstrates once again that reproducibility and review are important pillars of academic research. Therefore, we provide the reader with an online Python notebook which allows to reproduce some of our experiments1 and additional example code is made available on Github.2

scholarly journals Electromagnetic and Power Side-Channel Analysis: Advanced Attacks and Low-Overhead Generic Countermeasures through White-Box Approach

Cryptography ◽  
2020 ◽  
Vol 4 (4) ◽  
pp. 30
Author(s):  
Debayan Das ◽  
Shreyas Sen
Keyword(s):  
Deep Learning ◽  
State Of The Art ◽  
Side Channel ◽  
Secret Key ◽  
Embedded Devices ◽  
Side Channel Analysis ◽  
Root Cause ◽  
Channel Analysis ◽  
Metal Layers ◽  
A Current

Electromagnetic and power side-channel analysis (SCA) provides attackers a prominent tool to extract the secret key from the cryptographic engine. In this article, we present our cross-device deep learning (DL)-based side-channel attack (X-DeepSCA) which reduces the time to attack on embedded devices, thereby increasing the threat surface significantly. Consequently, with the knowledge of such advanced attacks, we performed a ground-up white-box analysis of the crypto IC to root-cause the source of the electromagnetic (EM) side-channel leakage. Equipped with the understanding that the higher-level metals significantly contribute to the EM leakage, we present STELLAR, which proposes to route the crypto core within the lower metals and then embed it within a current-domain signature attenuation (CDSA) hardware to ensure that the critical correlated signature gets suppressed before it reaches the top-level metal layers. CDSA-AES256 with local lower metal routing was fabricated in a TSMC 65 nm process and evaluated against different profiled and non-profiled attacks, showing protection beyond 1B encryptions, compared to ∼10K for the unprotected AES. Overall, the presented countermeasure achieved a 100× improvement over the state-of-the-art countermeasures available, with comparable power/area overheads and without any performance degradation. Moreover, it is a generic countermeasure and can be used to protect any crypto cores while preserving the legacy of the existing implementations.

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