Design Time Engineering of Side Channel Resistant Cipher Implementations

2013 ◽  
pp. 133-157 ◽  
Author(s):  
Alessandro Barenghi ◽  
Luca Breveglieri ◽  
Fabrizio De Santis ◽  
Filippo Melzani ◽  
Andrea Palomba ◽  
...  
Keyword(s):  
Power Consumption ◽  
Information Leakage ◽  
Smart Phones ◽  
Mobile Systems ◽  
Side Channel ◽  
Security Level ◽  
Embedded Devices ◽  
Design Time ◽  
Secret Keys ◽  
Channel Information

Dependable and trustworthy security solutions have emerged as a crucial requirement in the specification of the applications and protocols employed in modern Information Systems (IS). Threats to the security of embedded devices, such as smart phones and PDAs, have been growing since several techniques exploiting side-channel information leakage have proven successful in recovering secret keys even from complex mobile systems. This chapter summarizes the side-channel techniques based on power consumption and elaborates the issue of the design time engineering of a secure system, through the employment of the current hardware design tools. The results of the analysis show how these tools can be effectively used to understand possible vulnerabilities to power consumption side-channel attacks, thus providing a sound conservative margin on the security level. The possible extension of this methodology to the case of fault attacks is also sketched.

scholarly journals Comprehensive Evaluation on an ID-Based Side-Channel Authentication with FPGA-Based AES

2018 ◽  
Vol 8 (10) ◽  
pp. 1898 ◽  
Author(s):  
Yang Li ◽  
Momoka Kasuya ◽  
Kazuo Sakiyama
Keyword(s):  
Comprehensive Evaluation ◽  
Electronic Devices ◽  
Authentication Scheme ◽  
Side Channel ◽  
Silicon Chips ◽  
Secret Keys ◽  
Channel Information ◽  
Authentication Schemes ◽  
Speed And Accuracy ◽  
Comprehensive Study

Various electronic devices are increasingly being connected to the Internet. Meanwhile, security problems, such as fake silicon chips, still exist. The significance of verifying the authenticity of these devices has led to the proposal of side-channel authentication. Side-channel authentication is a promising technique for enriching digital authentication schemes. Motivated by the fact that each cryptographic device leaks side-channel information depending on its used secret keys, cryptographic devices with different keys can be distinguished by analyzing the side-channel information leaked during their calculation. Based on the original side-channel authentication scheme, this paper adapts an ID-based authentication scheme that can significantly increase the authentication speed compared to conventional schemes. A comprehensive study is also conducted on the proposed ID-based side-channel authentication scheme. The performance of the proposed authentication scheme is evaluated in terms of speed and accuracy based on an FPGA-based AES implementation. With the proposed scheme, our experimental setup can verify the authenticity of a prover among 2 70 different provers within 0.59 s; this could not be handled effectively using previous schemes.

A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture

2018 ◽  
Vol 23 (5) ◽  
pp. 1-30 ◽  
Author(s):  
Davide Zoni ◽  
Alessandro Barenghi ◽  
Gerardo Pelosi ◽  
William Fornaciari
Keyword(s):  
Information Leakage ◽  
Side Channel ◽  
Channel Information

scholarly journals Attacking and Defending Masked Polynomial Comparison for Lattice-Based Cryptography

2021 ◽  
pp. 334-359
Author(s):  
Shivam Bhasin ◽  
Jan-Pieter D’Anvers ◽  
Daniel Heinz ◽  
Thomas Pöppelmann ◽  
Michiel Van Beirendonck
Keyword(s):  
Information Leakage ◽  
Side Channel ◽  
Side Channel Attacks ◽  
First Order ◽  
Comparison Operation ◽  
Security Properties ◽  
Channel Information ◽  
Comparison Algorithms ◽  
Lattice Based Cryptography ◽  
Do So

In this work, we are concerned with the hardening of post-quantum key encapsulation mechanisms (KEM) against side-channel attacks, with a focus on the comparison operation required for the Fujisaki-Okamoto (FO) transform. We identify critical vulnerabilities in two proposals for masked comparison and successfully attack the masked comparison algorithms from TCHES 2018 and TCHES 2020. To do so, we use first-order side-channel attacks and show that the advertised security properties do not hold. Additionally, we break the higher-order secured masked comparison from TCHES 2020 using a collision attack, which does not require side-channel information. To enable implementers to spot such flaws in the implementation or underlying algorithms, we propose a framework that is designed to test the re-encryption step of the FO transform for information leakage. Our framework relies on a specifically parametrized t-test and would have identified the previously mentioned flaws in the masked comparison. Our framework can be used to test both the comparison itself and the full decapsulation implementation.

scholarly journals Towards Efficient and Automated Side Channel Evaluations at Design Time

10.29007/mbf3 ◽  
2018 ◽  
Author(s):  
Danilo Šijačić ◽  
Josep Balasch ◽  
Bohan Yang ◽  
Santosh Ghosh ◽  
Ingrid Verbauwhede
Keyword(s):  
Experimental Validation ◽  
State Of The Art ◽  
Information Leakage ◽  
Design Flow ◽  
Side Channel ◽  
Cell Design ◽  
Standard Cell ◽  
Side Channel Analysis ◽  
Design Time ◽  
Channel Analysis

Models and tools developed by the semiconductor community have matured over decades of use. As a result, hardware simulations can yield highly accurate and easily automated pre-silicon estimates for e.g. timing and area figures. In this work we design, implement, and evaluate CASCADE, a framework that combines a largely automated full-stack standard-cell design flow with the state of the art techniques for side channel analysis. We show how it can be used to efficiently evaluate side channel leakage prior to chip manufacturing. Moreover, it is independent of the underlying countermeasure and it can be applied starting from the earliest stages of the design flow. Additionally, we provide experimental validation through assessment of the side channel security of representative cryptographic circuits. We discuss aspects related to the performance, scalability, and utility to the designers. In particular, we show that CASCADE can evaluate information leakage with 1 million simulated traces in less than 4 hours using a single desktop workstation, for a design larger than 100kGE.

Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage

2014 ◽  
Vol E97.C (4) ◽  
pp. 272-279 ◽  
Author(s):  
Daisuke FUJIMOTO ◽  
Noriyuki MIURA ◽  
Makoto NAGATA ◽  
Yuichi HAYASHI ◽  
Naofumi HOMMA ◽  
...  
Keyword(s):  
Information Leakage ◽  
Vlsi Circuits ◽  
Side Channel ◽  
Noise Measurements ◽  
Channel Information ◽  
Power Noise

scholarly journals Information Theoretic Security for Broadcasting of Two Encrypted Sources under Side-Channel Attacks †

Entropy ◽  
2019 ◽  
Vol 21 (8) ◽  
pp. 781
Author(s):  
Bagus Santoso ◽  
Yasutada Oohama
Keyword(s):  
Secure Communication ◽  
Side Information ◽  
Physical Phenomenon ◽  
Sufficient Conditions ◽  
Information Leakage ◽  
Side Channel ◽  
Side Channel Attacks ◽  
Additional Information ◽  
Side Channels ◽  
Secret Keys

In this paper, we propose a theoretical framework to analyze the secure communication problem for broadcasting two encrypted sources in the presence of an adversary which launches side-channel attacks. The adversary is not only allowed to eavesdrop the ciphertexts in the public communication channel, but is also allowed to gather additional information on the secret keys via the side-channels, physical phenomenon leaked by the encryption devices during the encryption process, such as the fluctuations of power consumption, heat, or electromagnetic radiation generated by the encryption devices. Based on our framework, we propose a countermeasure against such adversary by using the post-encryption-compression (PEC) paradigm, in the case of one-time-pad encryption. We implement the PEC paradigm using affine encoders constructed from linear encoders and derive the explicit the sufficient conditions to attain the exponential decay of the information leakage as the block lengths of encrypted sources become large. One interesting feature of the proposed countermeasure is that its performance is independent from the type of side information leaked by the encryption devices.

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