UTILIZATION OF HIGH-SPEED DSP ALGORITHMS OF CYCLIC REDUNDANCY CHECKING (CRC-15) ENCODER AND DECODER FOR CONTROLLER AREA NETWORK

2016 ◽  
Vol 78 (5-9) ◽  
Author(s):  
Ronnie O. Serfa Juan ◽  
Hi Seok Kim
Keyword(s):  
Error Detection ◽  
High Speed ◽  
Clock Synchronization ◽  
Transmission Rate ◽  
Critical Path ◽  
Low Cost ◽  
Digital Signal ◽  
Transmission Error ◽  
Controller Area Network ◽  
Area Network

Advanced driver assistance system (ADAS) performs an increasing improvement in active road safety and driving convenience. Controller Area Network (CAN) is now getting popular because of its expanding applications and widely utilizations in low-cost embedded systems from automation to medical industry. While implementing an effective and efficient mechanism for clock synchronization, serial operation causes the reduction of CAN transmission rate can have an adverse impact on the real-time applications of systems employing this protocol. Also, maintaining the reliability of this technology especially in safety services, a reliable system needs certain requirements like glitches management and troubleshooting in order to avoid certain occurrences of transmission error.  In this paper we present a simulated Cyclic Redundancy Checking (CRC) encoder and decoder that perform high speed error detection for CAN using CRC-15. Digital Signal Processing (DSP) algorithms were used, namely pipelining, unfolding and retiming to attain the feasible iteration bound and critical path that is appropriate for CAN system. The source code for Encoder and Decoder has been formulated in Verilog Hardware Description Language (HDL) from actual simulation to implementation of this CRC-15 for CAN system.

scholarly journals A Review of Self-Coherent Optical Transceivers: Fundamental Issues, Recent Advances, and Research Directions

2021 ◽  
Vol 11 (16) ◽  
pp. 7554
Author(s):  
Isiaka Alimi ◽  
Romil Patel ◽  
Nuno Silva ◽  
Chuanbowen Sun ◽  
Honglin Ji ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Dynamic Environment ◽  
Digital Signal ◽  
Research Directions ◽  
Recent Advances ◽  
Heterogeneous Nature ◽  
Signal Processing Algorithms ◽  
Processing Algorithms

This paper reviews recent progress on different high-speed optical short- and medium-reach transmission systems. Furthermore, a comprehensive tutorial on high-performance, low-cost, and advanced optical transceiver (TRx) paradigms is presented. In this context, recent advances in high-performance digital signal processing algorithms and innovative optoelectronic components are extensively discussed. Moreover, based on the growing increase in the dynamic environment and the heterogeneous nature of different applications and services to be supported by the systems, we discuss the reconfigurable and sliceable TRxs that can be employed. The associated technical challenges of various system algorithms are reviewed, and we proffer viable solutions to address them.

Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems

2019 ◽  
Vol 28 (09) ◽  
pp. 1950149
Author(s):  
Bahram Rashidi ◽  
Mohammad Abedini
Keyword(s):  
High Speed ◽  
Critical Path ◽  
Low Cost ◽  
Path Delay ◽  
Point Multiplication ◽  
Low Area ◽  
Elliptic Curve Cryptosystems ◽  
Edwards Curves ◽  
Special Cases ◽  
Field Multiplication

This paper presents efficient lightweight hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on general and special cases of binary Edwards curves. The complete differential addition formulas have the cost of [Formula: see text] and [Formula: see text] for general and special cases of BECs, respectively, where [Formula: see text] and [Formula: see text] denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of BECs, the structure is implemented based on 3 concurrent multipliers. Also in the special case of BECs, two structures by employing 3 and 2 field multipliers are proposed for achieving the highest degree of parallelization and utilization of resources, respectively. The field multipliers are implemented based on the proposed efficient digit–digit polynomial basis multiplier. Two input operands of the multiplier proceed in digit level. This property leads to reduce hardware consumption and critical path delay. Also, in the structure, based on the change of input digit size from low digit size to high digit size the number of clock cycles and input words are different. Therefore, the multiplier can be flexible for different cryptographic considerations such as low-area and high-speed implementations. The point multiplication computation requires field inversion, therefore, we use a low-cost Extended Euclidean Algorithm (EEA) based inversion for implementation of this field operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX110 FPGA for two fields [Formula: see text] and [Formula: see text] are achieved. The results show improvements in terms of area and efficiency for the proposed structures compared to previous works.

High Speed Radio over Fiber System for Wireless Local Area Networks by Incorporating Alternate Mark Inversion Scheme

2018 ◽  
Vol 0 (0) ◽  
Author(s):  
Abhishek Sharma ◽  
Priyanka Chauhan
Keyword(s):  
High Speed ◽  
Transmission Rate ◽  
Low Cost ◽  
Wave Length ◽  
Local Area Networks ◽  
Local Area ◽  
Radio Over Fiber ◽  
Wireless Local Area Networks ◽  
Fiber System ◽  
High Data

Abstract Radio over fiber (RoF) technique has revolutionized communication industry with its high data transmission rate and ability to carry the radio signal with speed of light. It finds its application in wireless local area networks (WLANs) due to easy of deployment and low cost. This paper utilizes alternate mark inversion (AMI) technique in wave length division multiplexing (WDM) scheme to further enhance data carrying capacity of the system. It is observed that proposed AMI-WDM scheme is better technique for providing high data rates and is confirmed via SNR, Q factor and eye diagrams.

An Optimized FPGA Implementation of CAN 2.0 Protocol Error Detection Circuitry

2017 ◽  
Vol 6 (3) ◽  
pp. 602
Author(s):  
Md Farukh Hashmi ◽  
Avinash G. Keskar
Keyword(s):  
Embedded System ◽  
Data Storage ◽  
Error Detection ◽  
Low Cost ◽  
Disk Drive ◽  
Critical Issue ◽  
Subsequent Treatment ◽  
Area Network ◽  
Reconfigurable Platform ◽  
Vhdl Code

Controller Area Network is an ideal serial bus design suitable for modern embedded system based networks. It finds its use in most of critical applications, where error detection and subsequent treatment on error is a critical issue. CRC (Cyclic Redundancy Check) block was developed on FPGA in order to meet the needs for simple, low power and low cost wireless communication. This paper gives a short overview of CRC block in the Digital transmitter based on the CAN 2.0 protocols. CRC is the most preferred method of encoding because it provides very efficient protection against commonly occurring burst errors, and is easily implemented. This technique is also sometimes applied to data storage devices, such as a disk drive. In this paper a technique to model the error detection circuitry of CAN 2.0 protocols on reconfigurable platform have been discussed? The software simulation results are presented in the form of timing diagram.FPGA implementation results shows that the circuitry requires very small amount of digital hardware. The Purpose of the research is to diversify the design methods by using VHDL code entry through Modelsim 5.5e simulator and Xilinx ISE8.3i.The VHDL code is used to characterize the CRC block behavior which is then simulated, synthesized and successfully implemented on Sparten3 FPGA .Here, Simulation and Synthesized results are also presented to verify the functionality of the CRC -16 Block. The data rate of CRC block is 250 kbps .Estimated power consumption and maximum operating frequency of the circuitry is also provided.

scholarly journals Decimation of Delta-Sigma-Modulated Signals Using a Low-Cost Microcontroller

2021 ◽  
Author(s):  
Markeljan Fishta ◽  
Franco Fiori
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Experimental Tests ◽  
General Purpose ◽  
Data Conversion ◽  
Clock Frequency ◽  
Main Challenge ◽  
Modulated Signals

Abstract$$\varDelta \varSigma $$ Δ Σ analog-to-digital converters (ADCs) are largely used in sensor acquisition applications. In the last few years, standalone $$\varDelta \varSigma $$ Δ Σ modulators have become increasingly available as off-the-shelf parts. To build a complete ADC, a standalone modulator has to be paired with some advanced elaboration unit, such as a field programmable gate array (FPGA) or a digital signal processor (DSP), which is needed for the implementation of the decimation filter. This work investigates the use of low-cost, general-purpose microcontrollers for the decimation of $$\varDelta \varSigma $$ Δ Σ -modulated signals. The main challenge is given by the clock frequency of the modulator, which can be in the range of a few $$\hbox {MHz}$$ MHz . The proposed technique deals with this limitation by employing two serial peripheral interface (SPI) modules in a time-interleaved configuration. This approach allows for continuous acquisition and elaboration of relatively high-speed, digital signals. The technique has been applied to a case study, and a data conversion system has been practically realized. The performance of the proposed filter is compared to that of a digital filter, present on board a commercial microcontroller, and the results of experimental tests are provided.

PC104 Interface Recommended for High Speed Data Acquisition Systems

2013 ◽  
Vol 325-326 ◽  
pp. 926-929 ◽  
Author(s):  
Dorina Purcaru ◽  
Cornelia Gordan ◽  
Romulus Reiz ◽  
Anca Purcaru
Keyword(s):  
Data Acquisition ◽  
High Speed ◽  
Low Cost ◽  
Sampling Rate ◽  
Digital Signal ◽  
Signal Acquisition ◽  
Synchronized Sampling ◽  
Data Acquisition Systems ◽  
High Speed Data Acquisition ◽  
High Speed Data

The interface presented in this paper is recommended for high speed data acquisition systems; it performs a synchronized sampling of all common-mode or differential analog inputs with a high sampling rate. This is a low cost interface, entirely controlled by the PC104 CPU. Programmable electronic modules that contain such PC104 interfaces can be found running in the energetic system from Romania; these dedicated equipments perform the analog and digital signal acquisition for monitoring and recording different specific transient events. Some experimental results obtained using the disturbance monitoring device PC-08/104 are also presented in this paper.

scholarly journals IMPLEMENTATION OF HIGH SPEED-LOW POWER TRUNCATION ERROR TOLERANT ADDER

2015 ◽  
pp. 239-244
Author(s):  
SYAM KUMAR NAGENDLA ◽  
K. MIRANJI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Processing System ◽  
Digital Signal ◽  
Signal Processing System ◽  
Speed Performance ◽  
Power Delay Product ◽  
Dsp Systems

Now a Days in modern VLSI technology different kinds of errors are invitable. A new type of adder i.e. error tolerant adder(ETA) is proposed to tolerate those errors and to attain low power consumption and high speed performance in DSP systems. In conventional adder circuit, delay is mainly certified to the carry propagation chain along the critical path, from the LSB to MSB. If the carry propagation can be eliminated by the technique proposed in this paper, a great improvement in speed performance and power consumption is achieved. By operating shifting and addition in parallel, the error tolerant adder tree compensates for the truncation errors. To prove the feasibility of the ETA, normal addition operation present in the DFT or DCT algorithm is replaced by the proposed addition arithmetic and the experimental results are shown. In this paper we propose error tolerant Adder (ETA). In the view of DSP applications the ETA is able to case the strict restriction on accuracy, speed performance and power consumption when compared to the conventional Adders, the proposed one provides 76% improvement in power-delay product such a ETA plays a key role in digital signal processing system that can tolerate certain amount of errors.

Design of High-Speed Decoder for New High-Speed Bus

2010 ◽  
Vol 20-23 ◽  
pp. 958-962
Author(s):  
Wei Gong Zhang ◽  
Bo Yang ◽  
Rui Ding ◽  
Yong Qin Hu
Keyword(s):  
Error Correction ◽  
Intelligent Control ◽  
Error Detection ◽  
High Speed ◽  
Critical Path ◽  
Speed Error ◽  
Error Detection And Correction ◽  
Traditional Algorithm ◽  
New Type ◽  
Correction System

This paper presents a new type of high-speed error correction for the requirements of new high-Speed Bus. Use RS (255, 239). Not only optimization traditional algorithm, but also design bidirectional synchronous calculated adjoint form module, Fast B-M algorithm module. and full parallel Chien Search module. These design used in new high-Speed Bus, Larger than usual decoder designed to significantly shorten the critical path decoding, and achieve continuous decoding. In addition, this error correction system separated error detection and correction module modules, And after error detection module add intelligent control, which reduced the complexity and power consumption of equipment. The error correction system design for the requirements of the new bus which speed is above 400m / s.

The Motion Control System of Servomotor Based on CAN Bus

2012 ◽  
Vol 163 ◽  
pp. 260-263
Author(s):  
Jing Lin Tong ◽  
Bo Li ◽  
Xiao Bo Wang
Keyword(s):  
Control System ◽  
Motion Control ◽  
High Speed ◽  
Can Bus ◽  
High Reliability ◽  
Controller Area Network ◽  
Area Network ◽  
Price Ratio ◽  
Motion Control System ◽  
Communication Software

This paper introduces the hardware and the communication software design of control system based on Controller Area Network bus. The control system can realize to control the motion of servomotor through high speed C8501F040 single chip microcomputer with Controller Area Network bus and special motion controller - LM628. This system possesses characteristics such as simple structure, high reliability and high performance/price ratio. Key words: CAN bus, LM628, Motion Control System, Communication software

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