A Coarse-Grain Dynamically Reconfigurable System and Compilation Framework

Author(s):  
Marcos Sanchez-Elez ◽  
Milagros Fernandez ◽  
Nader Bagherzadeh ◽  
Roman Hermida ◽  
Fadi Kurdahi ◽  
...  
2010 ◽  
Vol 2010 ◽  
pp. 1-11 ◽  
Author(s):  
Stephanie Drzevitzky ◽  
Uwe Kastens ◽  
Marco Platzner

Dynamically reconfigurable hardware combines hardware performance with software-like flexibility and finds increasing use in networked systems. The capability to load hardware modules at runtime provides these systems with an unparalleled degree of adaptivity but at the same time poses new challenges for security and safety. In this paper, we elaborate on the presentation of proof carrying hardware (PCH) as a novel approach to reconfigurable system security. PCH takes a key concept from software security, known as proof-carrying code, into the reconfigurable hardware domain. We outline the PCH concept and discuss runtime combinational equivalence checking as a first online verification problem applying the concept. We present a prototype tool flow and experimental results demonstrating the feasibility and potential of the PCH approach.


2009 ◽  
Vol 4 (1) ◽  
pp. 36-44
Author(s):  
Julien Lallet ◽  
Sébastien Pillement ◽  
Olivier Sentieys

Dynamic reconfiguration is possible on both fine-grain and coarse-grain architectures. One of the used methodology used consists in the use of multi-context architectures. Unfortunately, the multiple contexts bring power and area overhead. This paper introduces the Dynamic Unifier and reConfigurable blocK (DUCK) concept, a new structure to perform efficiently dynamic reconfiguration on both custom designed fine-grain and coarse grain architectures. The DUCK allows to separate the configuration path and the configuration registers which facilitates simultaneous configuration and computing steps. The reconfiguration process is presented in detail, and synthesis results are given for different structures. Our solution is finally validated with the implementation of a WCDMA (Wideband Code Division Multiple Access) receiver on a multi-context embedded FPGA and on the dynamically reconfigurable processor DART. This implementation demonstrates the interest and the efficiency of the use of dynamic reconfiguration and the proposed flexible structure.


Author(s):  
Yuanqing Guo ◽  
Gerard J.M. Smit ◽  
Michèl A.J. Rosien ◽  
Paul M. Heysters ◽  
Thijs Krol ◽  
...  

Author(s):  
David De La Fuente ◽  
Jesus Barba ◽  
Xerach Pena ◽  
Juan Carlos Lopez ◽  
Pablo Penil ◽  
...  

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