Trace, Norm, and Bit-Serial Multiplication

Division and bit-serial multiplication over GF(qm)

IEE Proceedings E Computers and Digital Techniques ◽

10.1049/ip-e.1992.0036 ◽

1992 ◽

Vol 139 (3) ◽

pp. 230 ◽

Cited By ~ 27

Author(s):

M.A. Hasan ◽

V.K. Bhargava

Keyword(s):

Bit Serial

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Bit-serial systolic sorting: general complexities and an implementation in VLSI

IEE Proceedings E Computers and Digital Techniques ◽

10.1049/ip-e.1987.0022 ◽

1987 ◽

Vol 134 (3) ◽

pp. 125

Author(s):

H.F. Li ◽

R. Jayakumar ◽

X. Sun

Keyword(s):

Bit Serial

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Six shades lighter: a bit-serial implementation of the AES family

Journal of Cryptographic Engineering ◽

10.1007/s13389-021-00265-8 ◽

2021 ◽

Author(s):

Sergio Roldán Lombardía ◽

Fatih Balli ◽

Subhadeep Banik

Keyword(s):

Block Cipher ◽

Block Ciphers ◽

Authenticated Encryption ◽

Current Standard ◽

Asic Circuit ◽

The Family ◽

Encryption And Decryption ◽

Preliminary Version ◽

Reduction In Area ◽

Bit Serial

AbstractRecently, cryptographic literature has seen new block cipher designs such as , or that aim to be more lightweight than the current standard, i.e., . Even though family of block ciphers were designed two decades ago, they still remain as the de facto encryption standard, with being the most widely deployed variant. In this work, we revisit the combined one-in-all implementation of the family, namely both encryption and decryption of each as a single ASIC circuit. A preliminary version appeared in Africacrypt 2019 by Balli and Banik, where the authors design a byte-serial circuit with such functionality. We improve on their work by reducing the size of the compact circuit to 2268 GE through 1-bit-serial implementation, which achieves 38% reduction in area. We also report stand-alone bit-serial versions of the circuit, targeting only a subset of modes and versions, e.g., and . Our results imply that, in terms of area, and can easily compete with the larger members of recently designed family, e.g., , . Thus, our implementations can be used interchangeably inside authenticated encryption candidates such as , or in place of .

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Clipped Matrix Completion: A Remedy for Ceiling Effects

Proceedings of the AAAI Conference on Artificial Intelligence ◽

10.1609/aaai.v33i01.33015151 ◽

2019 ◽

Vol 33 ◽

pp. 5151-5158

Author(s):

Takeshi Teshima ◽

Miao Xu ◽

Issei Sato ◽

Masashi Sugiyama

Keyword(s):

Matrix Completion ◽

Low Rank ◽

Trace Norm ◽

Minimization Algorithm ◽

Benchmark Data ◽

Hinge Loss ◽

Norm Minimization ◽

Rank Matrix ◽

Recovery Error ◽

Low Rank Matrix

We consider the problem of recovering a low-rank matrix from its clipped observations. Clipping is conceivable in many scientific areas that obstructs statistical analyses. On the other hand, matrix completion (MC) methods can recover a low-rank matrix from various information deficits by using the principle of low-rank completion. However, the current theoretical guarantees for low-rank MC do not apply to clipped matrices, as the deficit depends on the underlying values. Therefore, the feasibility of clipped matrix completion (CMC) is not trivial. In this paper, we first provide a theoretical guarantee for the exact recovery of CMC by using a trace-norm minimization algorithm. Furthermore, we propose practical CMC algorithms by extending ordinary MC methods. Our extension is to use the squared hinge loss in place of the squared loss for reducing the penalty of overestimation on clipped entries. We also propose a novel regularization term tailored for CMC. It is a combination of two trace-norm terms, and we theoretically bound the recovery error under the regularization. We demonstrate the effectiveness of the proposed methods through experiments using both synthetic and benchmark data for recommendation systems.

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