pipelined architecture
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Author(s):  
Anita P. ◽  
Manju Devi

The packet classification plays a significant role in many network systems, which requires the incoming packets to be categorized into different flows and must take specific actions as per functional and application requirements. The network system speed is continuously increasing, so the demand for the packet classifier also increased. Also, the packet classifier's complexity is increased further due to multiple fields should match against a large number of rules. In this manuscript, an efficient and high performance modified bitvector (MBV) based packet classification (PC) is designed and implemented on low-cost Artix-7 FPGA. The proposed MBV based PC employs pipelined architecture, which offers low latency and high throughput for PC. The MBV based PC utilizes <2% slices, operating at 493.102 MHz, and consumes 0.1 W total power on Artix-7 FPGA. The proposed PC considers only 4 clock cycles to classify the incoming packets and provides 74.95 Gbps throughput. The comparative results in terms of hardware utilization and performance efficiency of proposed work with existing similar PC approaches are analyzed with better constraints improvement.


2021 ◽  
Author(s):  
jiaqi Jiang ◽  
jiahai Dai ◽  
hongbo Zhang ◽  
yusong Mu ◽  
yuchun Chang

Abstract To improve the subdivision accuracy of a photoelectric encoder and reduce the effects of sinusoidal errors in the signals on the measurement accuracy of the system, we designed an optoelectronic chip to receive grating moiré fringe signals. An amplifier circuit with a hierarchical pipelined architecture was designed, and the photodetector array was matched with the code disk before processing the received signals. Thereafter, a quantitative analysis was performed on the sinusoidal errors in the signals. From the analysis results, a sinusoidal error compensation method based on the particle swarm optimization (PSO) algorithm was developed, and a subdivision error compensation model was established to correct the errors in the signals. Finally, a fast solution for the PSO algorithm was implemented on a field-programmable gate array, and a grating test platform was built for experimental verifications. The results showed that the peak-to-peak subdivision error of the encoder’s photoelectric signal decreased by approximately 60% from 2.98ʺ to 1.13ʺ. Therefore, the scheme proposed in this paper is expected to significantly improve the measurement accuracies of photoelectric encoders.


Author(s):  
Zhe Han ◽  
Jingfei Jiang ◽  
Jinwei Xu ◽  
Peng Zhang ◽  
Xiaoqiang Zhao ◽  
...  

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