Six shades lighter: a bit-serial implementation of the AES family

Recently, cryptographic literature has seen new block cipher designs such as , or that aim to be more lightweight than the current standard, i.e., . Even though family of block ciphers were designed two decades ago, they still remain as the de facto encryption standard, with being the most widely deployed variant. In this work, we revisit the combined one-in-all implementation of the family, namely both encryption and decryption of each as a single ASIC circuit. A preliminary version appeared in Africacrypt 2019 by Balli and Banik, where the authors design a byte-serial circuit with such functionality. We improve on their work by reducing the size of the compact circuit to 2268 GE through 1-bit-serial implementation, which achieves 38% reduction in area. We also report stand-alone bit-serial versions of the circuit, targeting only a subset of modes and versions, e.g., and . Our results imply that, in terms of area, and can easily compete with the larger members of recently designed family, e.g., , . Thus, our implementations can be used interchangeably inside authenticated encryption candidates such as , or in place of .

A Low Complexity Joint Encryption-Modulation Method for IoT Sensor Transceivers

Physical layer encryption (PLE) is a new research trend for securing data in communication systems. However, conventional procedures in works on PLE are of high complexity and degrade the packet error rate (PER) performance of the system. They are therefore not yet suitable for IoT sensors’ transceiver, which has limited power and computational resource. In this paper, we propose a low complexity PLE method named as joint encryption-modulation (JEM) for small transceivers such as IoT sensors. In our JEM method, data is encrypted after modulation to preserve high security. Our JEM method does not make change the constellation of the modulation after encryption; therefore, the encryption does not degrade PER performance of the system as the conventional works do. Furthermore, the encryption is performed by XOR gates and multiplexers only. It is, therefore, low complexity. Our experiment results show that the JEM method improves about 3 dB of PER performance as compared with that of conventional works. JEM method can support multiple modulation types such as BPSK, QPSK, 16-256 QAM within a small hardware cost. Compared with conventional works, JEM’s hardware resource is reduced by 87.5% in terms of FPGA synthesis and 86.5% in terms of the ASIC circuit. ASIC static power consumption of JEM is reduced by 80.6%.

An intelligent power MOSFET driver ASIC circuit with additional integrated safety operation functionality

This paper presents an extension to the previously presented conference paper [1] a power MOSFET driver ASIC with intelligent driving algorithm approach of the power modern MOSFET devices. The intelligent driving algorithm concept proposes a realization of power MOSFET gate driving with controlled source/sink current of the power MOSFET driver circuit. Such approach enables higher control of the power MOSFET operation behavior, especially during switching events. Additionally to the previously published work this paper presents implementation of the intelligent driving algorithm and driver safety operation functions on a single integrated ASIC circuit. The paper concludes with presentation of some functions of the manufactured ASIC circuit in CMOS technology.