Analisis Keberlanjutan Usahatani Perkebunan Kelapa Rakyat Kabupaten Indragiri Hilir

Coconut plantation is one of the strategic commodities in the national economy and community welfare. The problems related to smallholding coconut farmers, namely the reduction in area and coconut production every year. Research needs to be conducted to determine the sustainability status of smallholings’ coconut farmer plantations through the MDS method bin Indragiri Hilir Regency. Data were collected from 45 respondents in each sub-district, namely Indragiri Hilir Regency, namely Enok, Keritang, Mandah, and Pulau Burung Districts, and analyzed with the Multidimensional Scalling (MDS) method covering economic, environmental and socio-cultural dimensions. Primary data were obtained from direct interviews with farmer respondents and several experts who concentrated on the coconut which were selected purposively, secondary data obtained from the Central Statistics Agency, Agriculture and Plantation Service, and other kinds of literature that support this research. The results of the ordination Rap-technique on the MDS method showed that the index value of the sustainability of the smallholder coconut plantations in Indragiri Hilir Regency ranged from 25,01 to 50,00 which was categorized as less sustainable. In particular, the sustainability index is 48.01, 33,76, and 28,06 for the economy, ecology and socio-culture, respectively. The sustainability of smallholdings’ coconut plantation farming in each dimension has a different sustainability index, the different sustainability index indicates a need for different policies to improve the sustainability status of smallholder coconut plantations in Indragiri Hilir Regency.

Enhancing the climate resilience of coffee production.

Climate change is adversely affecting coffee production, impacting both yields and quality. Coffee production is dominated by the cultivation of Arabica and Robusta coffee, species that represent 99% of production, but both species will be affected by climate change. Sustainable management practices that can enhance the resilience of production are urgently needed, as coffee production supports the livelihoods of over 25 million people across the world, the majority of whom are smallholder farmers located in the coffee belt spanning the tropics. We conducted a systematic review, identifying 78 studies that describe agro-ecological practices that have potential to enhance climate resilience. Adverse environmental impacts include a reduction in area suitable for production, lower yields, increased intensity and frequency of extreme climate events, and greater incidence of pests and diseases. Potential environmental solutions include altitudinal shifts, the introduction of new, more resilient cultivars, altering agrochemical inputs, and integrating agroforestry. However, financial, environmental and technical constraints limit the availability of many of these approaches to farmers, particularly smallholder producers. There is therefore an urgent need to address these barriers through appropriate policy mechanisms in order to continue meeting growing demand for coffee.

Numerical Simulation of the Hot Rolling Process of Steel Beams

The complete rolling schedule (25 passes) of steel beams in a mill was simulated to predict the final beam length, geometry of the cross-section, effective stress, effective plastic strain and rolling power for two cases; the first case corresponds to the hot rolling process assuming a constant temperature of 1200 ∘C. The simulation of the second case considered the real beam temperature at each pass to compare the results with in-plant measurements and validate the numerical model. Then, the results of both cases were compared to determine the critical passes of the process with high peaks of required power, coinciding with the reports at the mill. These critical passes share the same conditions, high percentage of reduction in cross-sectional area and low beam temperature. Additionally, a potential reduction of passes in the process was proposed identifying passes with low required power, minimal reduction in area of cross-section and essentially unchanged geometry. Therefore, it is reasonable to state that using the present research methodology, it is possible to have a better control of the process allowing innovation in the production of profiles with more complex geometries and new materials.

RRAM-based CAM combined with time-domain circuits for hyperdimensional computing

Content addressable memory (CAM) for search and match operations demands high speed and low power for near real-time decision-making across many critical domains. Resistive RAM (RRAM)-based in-memory computing has high potential in realizing an efficient static CAM for artificial intelligence tasks, especially on resource-constrained platforms. This paper presents an XNOR-based RRAM-CAM with a time-domain analog adder for efficient winning class computation. The CAM compares two operands, one voltage and the second one resistance, and outputs a voltage proportional to the similarity between the input query and the pre-stored patterns. Processing the summation of the output similarity voltages in the time-domain helps avoid voltage saturation, variation, and noise dominating the analog voltage-based computing. After that, to determine the winning class among the multiple classes, a digital realization is utilized to consider the class with the longest pulse width as the winning class. As a demonstrator, hyperdimensional computing for efficient MNIST classification is considered. The proposed design uses 65 nm CMOS foundry technology and realistic data for RRAM with total area of 0.0077 mm2, consumes 13.6 pJ of energy per 1 k query within 10 ns clock cycle. It shows a reduction of ~ 31 × in area and ~ 3 × in energy consumption compared to fully digital ASIC implementation using 65 nm foundry technology. The proposed design exhibits a remarkable reduction in area and energy compared to two of the state-of-the-art RRAM designs.

Changes in hunting season regulations (1870s–2019) reduce harvest exposure on greater and Gunnison sage-grouse

Hunter harvest is a potential factor contributing to population declines of sage-grouse (Centrocercus spp.). As a result, wildlife agencies throughout western North America have set increasingly more conservative harvest regulations over the past 25 years to reduce or eliminate hunter success and concomitant numbers of harvested greater (C. urophasianus) and Gunnison (C. minimus) sage-grouse. Sage-grouse hunting has varied widely over time and space, which has made a comprehensive summary of hunting management challenging. We compiled data on harvest regulations among 11 western U.S. states and 2 Canadian provinces from 1870–2019 to create a timeline representative of hunting regulations. We compared annual harvest boundaries and area-weighted average hunting regulations, 1995–2018, relative to administrative boundaries and areas of high probability of sage-grouse occupation. We also summarized estimated numbers of birds harvested and hunters afield, 1995–2018, across both species’ ranges. From 1995–2018, there was a 30% reduction in administrative harvest boundaries across the greater sage-grouse range compared to a 16.6% reduction in area open to harvest within 8 km from active leks. Temporary closures occurred in response to wildfires, disease outbreaks, low population numbers, and two research projects; whereas, permanent closures primarily occurred in small populations and areas on the periphery of the species distribution. Similarly, area-weighted possession limits and season length for greater sage-grouse decreased 52.6% and 61.0%, respectively, while season start date stayed relatively stable (mean start date ~259 [mid-September]). In contrast, hunting of the now federally-threatened Gunnison sage-grouse ended after 1999. While restrictions in harvest regulations were large in area, closures near areas of high greater sage-grouse occupancy were relatively smaller with the same trend for Gunnison sage-grouse until hunting ceased. For greater sage-grouse, most states reduced bag and possession limits and appeared to adhere to recommendations for later and shorter hunting seasons, reducing potential for additive mortality.

Area Efficient Modified Array Multiplier

Multipliers are widely used for various application like signal processing. Multipliers are used for multiplication two binary data .There are different kinds of multipliers with their own advantages and disadvantages. In this paper we implemented Array multiplier which has considerably more speed but also more area, it was implemented using pseudo NMOS logic in Cadence software and the number of transistors was reduced from 2N to N+1 which also lead to reduction in area.

RRAM-Based CAM Combined With Time-Domain Circuits for Hyperdimensional Computing

Content addressable memory (CAM) for search and match operations demands high speed and low power for near real-time decision-making across many critical domains. Resistive RAM-based in-memory computing has high potential in realizing an efficient static CAM for artificial intelligence tasks, especially on resource-constrained platforms. This paper presents an XNOR-based RRAM-CAM with a time-domain analog adder for efficient winning class computation. The CAM compares two operands, one voltage and the second one resistance, and outputs a voltage proportional to the similarity between the input query and the pre-stored patterns. Processing the summation of the output similarity voltages in the time-domain helps avoid voltage saturation, variation, and noise dominating the analog voltage-based computing. After that, to determine the winning class among the multiple classes, a digital realization is utilized to consider the class with the longest pulse width as the winning class. As a demonstrator, hyperdimensional computing for efficient MNIST classification is considered.The proposed design uses 65nm CMOS foundry technology and realistic data for RRAM with total area of 0.0077 mm2 , consumes 13.6 pJ of energy per 1k query within 10 ns clock cycle for 10 classes. It shows a reduction of ∼ 31× in area and ∼ 3× in energy consumption compared to fully digital ASIC implementation using 65nm foundry technology. The proposed design exhibits a remarkable reduction in area and energy compared to two of the state-of-the-art RRAM designs.

Six shades lighter: a bit-serial implementation of the AES family

Recently, cryptographic literature has seen new block cipher designs such as , or that aim to be more lightweight than the current standard, i.e., . Even though family of block ciphers were designed two decades ago, they still remain as the de facto encryption standard, with being the most widely deployed variant. In this work, we revisit the combined one-in-all implementation of the family, namely both encryption and decryption of each as a single ASIC circuit. A preliminary version appeared in Africacrypt 2019 by Balli and Banik, where the authors design a byte-serial circuit with such functionality. We improve on their work by reducing the size of the compact circuit to 2268 GE through 1-bit-serial implementation, which achieves 38% reduction in area. We also report stand-alone bit-serial versions of the circuit, targeting only a subset of modes and versions, e.g., and . Our results imply that, in terms of area, and can easily compete with the larger members of recently designed family, e.g., , . Thus, our implementations can be used interchangeably inside authenticated encryption candidates such as , or in place of .

Carry-Propagation-Adder-Factored Gemmini Systolic Array for Machine Learning Acceleration

Systolic arrays are the primary part of modern deep learning accelerators and are being used widely in real-life applications such as self-driving cars. This paper presents a novel factored systolic array, where the carry propagation adder for accumulation and the rounding logic are extracted out from each processing element, which reduces the area, power and delay of the processing elements substantially. The factoring is performed in the column-wise manner and the cost of the factored logic, placed at each column output, is amortized by the processing elements in a column. We demonstrate the proposed factoring in an open source systolic array, Gemmini. The factoring technique does not change the functionality of the base design and is transparent to applications. We show that the proposed technique leads to substantial reduction in area and delay up to 45.3% and 23.7%, respectively, compared to the Gemmini baseline.