Global Routing

1993 ◽  
pp. 205-245
Author(s):  
Naveed A. Sherwani
Keyword(s):  
Global Routing

Hierarchical detailed floorplanning with global routing in VLSI layout design

1991 ◽  
Vol 74 (10) ◽  
pp. 85-95
Author(s):  
Michiroh Ohmura ◽  
Shin'Ichi Wakabayashi ◽  
Jun'Ichi Miyao ◽  
Noriyoshi Yoshida
Keyword(s):  
Layout Design ◽  
Global Routing ◽  
Vlsi Layout

A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem

2005 ◽  
Author(s):  
Tong Jing ◽  
Ling Zhang ◽  
Jinghong Liang ◽  
Jingyu Xu ◽  
Xianlong Hong ◽  
...  
Keyword(s):  
Global Routing ◽  
Routing Problem

A New Global Routing Algorithm For FPGAs

2005 ◽  
Author(s):  
Yao-Wen Chang ◽  
S. Thakur ◽  
Kai Zhu ◽  
D.F. Wong
Keyword(s):  
Routing Algorithm ◽  
Global Routing

GRIP: Global Routing via Integer Programming

2011 ◽  
Vol 30 (1) ◽  
pp. 72-84 ◽  
Author(s):  
Tai-Hsuan Wu ◽  
Azadeh Davoodi ◽  
Jeffrey T. Linderoth
Keyword(s):  
Integer Programming ◽  
Global Routing

scholarly journals BEAR-FP: A ROBUST FRAMEWORK FOR FLOORPLANNING

1992 ◽  
Vol 03 (01) ◽  
pp. 137-170 ◽  
Author(s):  
MASSOUD PEDRAM ◽  
ERNEST S. KUH
Keyword(s):  
Shape Function ◽  
Optimization Procedure ◽  
University Of California ◽  
Global Routing ◽  
Top Down ◽  
Function Computation ◽  
Wide Range ◽  
The University ◽  
Linear Assignment ◽  
Selection Of

This paper presents a hierarchical floorplanning approach for macrocell layouts which is based on the bottom-up clustering, shape function computation, and top-down floorplan optimization with integrated global routing and pin assignment. This approach provides means for specifying and techniques for satisfying a wide range of constraints (physical, topological, timing) and is, therefore, able to generate floorplans for a number of different layout styles. A systematic and efficient optimization procedure during the selection of suitable floorplan patterns that integrates floorplanning, global routing and pin assignment, a new pin assignment technique based on linear assignment and driven by the global routing solution and floorplan topology, and an effective timing-driven floorplanning scheme are among the other novel features of the floorplanner. These techniques have been incorporated in BEAR-FP, a macrocell layout system developed at the University of California, Berkeley. Results on various placement and floorplanning benchmarks are quite good.

Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability

2008 ◽  
Author(s):  
Aseem Gupta ◽  
Nikil D. Dutt ◽  
Fadi J. Kurdahi ◽  
Kamal S. Khouri ◽  
Magdy S. Abadir
Keyword(s):  
Global Routing ◽  
Vlsi Chips
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