Wire length optimization of VLSI circuits using IWO algorithm and its hybrid

Purpose Advancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die where global routing problem remains significant with a trade-off of power dissipation and interconnect delay. This paper aims to solve the increased complexity in VLSI chip by minimization of the wire length in VLSI circuits using a new approach based on nature-inspired meta-heuristic, invasive weed optimization (IWO). Further, this paper aims to achieve maximum circuit optimization using IWO hybridized with particle swarm optimization (PSO). Design/methodology/approach This paper projects the complexities of global routing process of VLSI circuit design in mapping it with a well-known NP-complete problem, the minimum rectilinear Steiner tree (MRST) problem. IWO meta-heuristic algorithm is proposed to meet the MRST problem more efficiently and thereby reducing the overall wire-length of interconnected nodes. Further, the proposed approach is hybridized with PSO, and a comparative analysis is performed with geosteiner 5.0.1 and existing PSO technique over minimization, consistency and convergence against available benchmark. Findings This paper provides high performance–enhanced IWO algorithm, which keeps in generating low MRST value, thereby successful wire length reduction of VLSI circuits is significantly achieved as evident from the experimental results as compared to PSO algorithm and also generates value nearer to geosteiner 5.0.1 benchmark. Even with big VLSI instances, hybrid IWO with PSO establishes its robustness over achieving improved optimization of overall wire length of VLSI circuits. Practical implications This paper includes implications in the areas of optimization of VLSI circuit design specifically in the arena of VLSI routing and the recent developments in routing optimization using meta-heuristic algorithms. Originality/value This paper fulfills an identified need to study optimization of VLSI circuits where minimization of overall interconnected wire length in global routing plays a significant role. Use of nature-based meta-heuristics in solving the global routing problem is projected to be an alternative approach other than conventional method.

Rectilinear Steiner Tree Construction Techniques Using PB-SAT-Based Methodology

Rectilinear Steiner Tree (RST) construction is a fundamental problem in very large scale integration (VLSI) physical design. Its applications include placement and routing in VLSI physical design automation (PDA) where wire length and timing estimations for signal nets are obtained. In this paper, a pseudo-Boolean satisfiability (PB-SAT)-based approach is presented to solve rectilinear Steiner tree problem. But large nets are a bottleneck for any SAT-based approach. Hence, to deal with large nets, a region-partitioning-based algorithm is taken into consideration, which eventually achieves a reasonable running time. Furthermore, a clustering-based approach is also explored to improve the partitioning of nets by identifying clusters and then applying a heuristic-based approach to get the minimum wire length for each set of the clusters. Experimental results obtained by these techniques show that the proposed algorithm can solve the RST problem very effectively even on large circuits and it outperforms the widely used RST algorithm FLUTE with 3[Formula: see text][Formula: see text][Formula: see text]to 9[Formula: see text][Formula: see text][Formula: see text]speedups.